[thirdparty/u-boot.git] / include / configs / devkit8000.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2009
 * Frederik Kriewitz <frederik@kriewitz.eu>
 *
 * Configuration settings for the DevKit8000 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */

#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

/*  Physical Memory Map  */

#include <configs/ti_omap3_common.h>

#define CONFIG_REVISION_TAG		1

/* Size of malloc() pool */
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/* Hardware drivers */
/* DM9000 */
#define CONFIG_NET_RETRY_COUNT		20
#define	CONFIG_DRIVER_DM9000		1
#define	CONFIG_DM9000_BASE		0x2c000000
#define	DM9000_IO			CONFIG_DM9000_BASE
#define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
#define	CONFIG_DM9000_USE_16BIT		1
#define CONFIG_DM9000_NO_SROM		1
#undef	CONFIG_DM9000_DEBUG

/* TWL4030 */

/* Board NAND Info */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* BOOTP/DHCP options */
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_TIMEOFFSET
#undef CONFIG_BOOTP_VENDOREX

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	"kernelopts=rw\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay}\0" \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"rootwait " \
		"${kernelopts}\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=/dev/mtdblock4 " \
		"rootfstype=jffs2 " \
		"${kernelopts}\0" \
	"netargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/nfs " \
		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
		"${kernelopts} " \
		"dnsip1=${dnsip} " \
		"dnsip2=${dnsip2}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"netboot=echo Booting from network ...; " \
		"dhcp ${loadaddr}; " \
		"run netargs; " \
		"bootm ${loadaddr}\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"

#define CONFIG_BOOTCOMMAND "run autoboot"

/* Boot Argument Buffer Size */

/* SRAM config */
#define CONFIG_SYS_SRAM_START              0x40200000
#define CONFIG_SYS_SRAM_SIZE               0x10000

/* Defines for SPL */

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000

/* SPL OS boot options */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000

#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */

#undef CONFIG_SYS_SPL_ARGS_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c35d7cf0 FK	2	/*
	3	* (C) Copyright 2006-2008
	4	* Texas Instruments.
	5	* Richard Woodruff <r-woodruff2@ti.com>
	6	* Syed Mohammed Khasim <x0khasim@ti.com>
	7	*
	8	* (C) Copyright 2009
	9	* Frederik Kriewitz <frederik@kriewitz.eu>
	10	*
	11	* Configuration settings for the DevKit8000 board.
c35d7cf0 FK	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
c35d7cf0 FK	16
c35d7cf0 FK	17	/* High Level Configuration Options */
2d52a9a3	18	#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
308252ad	19
5183b7ec SS	20	/*
	21	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	22	* 64 bytes before this address should be set aside for u-boot.img's
	23	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	24	* other needs.
	25	*/
66fca016	26
875e4154 AB	27	#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
	28	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	29
	30	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	31	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
cae377b5	32
875e4154	33	/* Physical Memory Map */
875e4154	34
a91ef4ad	35	#include <configs/ti_omap3_common.h>
875e4154	36
c35d7cf0 FK	37	#define CONFIG_REVISION_TAG 1
	38
	39	/* Size of malloc() pool */
875e4154	40	#undef CONFIG_SYS_MALLOC_LEN
9c44ddcc	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
c35d7cf0 FK	42
c35d7cf0 FK	43	/* Hardware drivers */
c35d7cf0	44	/* DM9000 */
c35d7cf0 FK	45	#define CONFIG_NET_RETRY_COUNT 20
	46	#define CONFIG_DRIVER_DM9000 1
	47	#define CONFIG_DM9000_BASE 0x2c000000
	48	#define DM9000_IO CONFIG_DM9000_BASE
	49	#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
	50	#define CONFIG_DM9000_USE_16BIT 1
	51	#define CONFIG_DM9000_NO_SROM 1
	52	#undef CONFIG_DM9000_DEBUG
	53
c35d7cf0	54	/* TWL4030 */
c35d7cf0 FK	55
c35d7cf0 FK	56	/* Board NAND Info */
c35d7cf0 FK	57	#define CONFIG_JFFS2_NAND
	58	/* nand device jffs2 lives on */
	59	#define CONFIG_JFFS2_DEV "nand0"
	60	/* start of jffs2 partition */
	61	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	62	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	63	/* partition */
	64
c35d7cf0	65	/* BOOTP/DHCP options */
c35d7cf0	66	#define CONFIG_BOOTP_NISDOMAIN
c35d7cf0	67	#define CONFIG_BOOTP_BOOTFILESIZE
c35d7cf0 FK	68	#define CONFIG_BOOTP_DNS2
c35d7cf0 FK	69	#define CONFIG_BOOTP_SEND_HOSTNAME
c35d7cf0 FK	70	#define CONFIG_BOOTP_TIMEOFFSET
	71	#undef CONFIG_BOOTP_VENDOREX
	72
	73	/* Environment information */
c35d7cf0 FK	74	#define CONFIG_EXTRA_ENV_SETTINGS \
c35d7cf0 FK	75	"loadaddr=0x82000000\0" \
2d76da24	76	"console=ttyO2,115200n8\0" \
f408501d	77	"mmcdev=0\0" \
c35d7cf0 FK	78	"vram=12M\0" \
	79	"dvimode=1024x768MR-16@60\0" \
	80	"defaultdisplay=dvi\0" \
	81	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	82	"kernelopts=rw\0" \
	83	"commonargs=" \
	84	"setenv bootargs console=${console} " \
	85	"vram=${vram} " \
	86	"omapfb.mode=dvi:${dvimode} " \
	87	"omapdss.def_disp=${defaultdisplay}\0" \
	88	"mmcargs=" \
	89	"run commonargs; " \
	90	"setenv bootargs ${bootargs} " \
	91	"root=/dev/mmcblk0p2 " \
b72db208	92	"rootwait " \
c35d7cf0 FK	93	"${kernelopts}\0" \
	94	"nandargs=" \
	95	"run commonargs; " \
	96	"setenv bootargs ${bootargs} " \
	97	"omapfb.mode=dvi:${dvimode} " \
	98	"omapdss.def_disp=${defaultdisplay} " \
	99	"root=/dev/mtdblock4 " \
	100	"rootfstype=jffs2 " \
	101	"${kernelopts}\0" \
	102	"netargs=" \
	103	"run commonargs; " \
	104	"setenv bootargs ${bootargs} " \
	105	"root=/dev/nfs " \
	106	"nfsroot=${serverip}:${rootpath},${nfsopts} " \
	107	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
	108	"${kernelopts} " \
	109	"dnsip1=${dnsip} " \
	110	"dnsip2=${dnsip2}\0" \
f408501d	111	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
c35d7cf0 FK	112	"bootscript=echo Running bootscript from mmc ...; " \
c35d7cf0 FK	113	"source ${loadaddr}\0" \
f408501d	114	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
c35d7cf0 FK	115	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	116	"mmcboot=echo Booting from mmc ...; " \
	117	"run mmcargs; " \
	118	"bootm ${loadaddr}\0" \
	119	"nandboot=echo Booting from nand ...; " \
	120	"run nandargs; " \
	121	"nand read ${loadaddr} 280000 400000; " \
	122	"bootm ${loadaddr}\0" \
	123	"netboot=echo Booting from network ...; " \
	124	"dhcp ${loadaddr}; " \
	125	"run netargs; " \
	126	"bootm ${loadaddr}\0" \
66968110	127	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
c35d7cf0 FK	128	"if run loadbootscript; then " \
	129	"run bootscript; " \
	130	"else " \
	131	"if run loaduimage; then " \
	132	"run mmcboot; " \
	133	"else run nandboot; " \
	134	"fi; " \
	135	"fi; " \
	136	"else run nandboot; fi\0"
	137
c35d7cf0 FK	138	#define CONFIG_BOOTCOMMAND "run autoboot"
c35d7cf0 FK	139
c35d7cf0	140	/* Boot Argument Buffer Size */
c35d7cf0	141
3f6a4922 SS	142	/* SRAM config */
	143	#define CONFIG_SYS_SRAM_START 0x40200000
	144	#define CONFIG_SYS_SRAM_SIZE 0x10000
	145
	146	/* Defines for SPL */
3f6a4922	147
3f6a4922	148	/* NAND boot config */
c471ccb9	149	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
3f6a4922 SS	150	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	151	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	152	#define CONFIG_SYS_NAND_OOBSIZE 64
	153	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	154	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	155	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	156	10, 11, 12, 13}
	157
	158	#define CONFIG_SYS_NAND_ECCSIZE 512
	159	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	160	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
3f6a4922	161
3f6a4922 SS	162	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	163	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
	164
d38bc97d	165	/* SPL OS boot options */
d38bc97d	166	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
b6144dfc	167
875e4154 AB	168	#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
	169	#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
	170	#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
b6144dfc TR	171	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
	172	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
	173	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
	174
a91ef4ad	175	#undef CONFIG_SYS_SPL_ARGS_ADDR
d38bc97d SS	176	#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
d38bc97d SS	177
c35d7cf0	178	#endif /* __CONFIG_H */