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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c35d7cf0 FK |
2 | /* |
3 | * (C) Copyright 2006-2008 | |
4 | * Texas Instruments. | |
5 | * Richard Woodruff <r-woodruff2@ti.com> | |
6 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
7 | * | |
8 | * (C) Copyright 2009 | |
9 | * Frederik Kriewitz <frederik@kriewitz.eu> | |
10 | * | |
11 | * Configuration settings for the DevKit8000 board. | |
c35d7cf0 FK |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
c35d7cf0 FK |
16 | |
17 | /* High Level Configuration Options */ | |
2d52a9a3 | 18 | #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 |
308252ad | 19 | |
5183b7ec SS |
20 | /* |
21 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
22 | * 64 bytes before this address should be set aside for u-boot.img's | |
23 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
24 | * other needs. | |
25 | */ | |
66fca016 | 26 | |
875e4154 AB |
27 | #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ |
28 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
29 | ||
30 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
31 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ | |
cae377b5 | 32 | |
875e4154 AB |
33 | /* Physical Memory Map */ |
34 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
875e4154 | 35 | |
a91ef4ad | 36 | #include <configs/ti_omap3_common.h> |
875e4154 | 37 | |
c35d7cf0 FK |
38 | #define CONFIG_MISC_INIT_R |
39 | ||
c35d7cf0 FK |
40 | #define CONFIG_REVISION_TAG 1 |
41 | ||
42 | /* Size of malloc() pool */ | |
9c44ddcc | 43 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
c35d7cf0 | 44 | /* Sector */ |
875e4154 | 45 | #undef CONFIG_SYS_MALLOC_LEN |
9c44ddcc | 46 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
c35d7cf0 FK |
47 | |
48 | /* Hardware drivers */ | |
c35d7cf0 | 49 | /* DM9000 */ |
c35d7cf0 FK |
50 | #define CONFIG_NET_RETRY_COUNT 20 |
51 | #define CONFIG_DRIVER_DM9000 1 | |
52 | #define CONFIG_DM9000_BASE 0x2c000000 | |
53 | #define DM9000_IO CONFIG_DM9000_BASE | |
54 | #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) | |
55 | #define CONFIG_DM9000_USE_16BIT 1 | |
56 | #define CONFIG_DM9000_NO_SROM 1 | |
57 | #undef CONFIG_DM9000_DEBUG | |
58 | ||
c35d7cf0 | 59 | /* TWL4030 */ |
c35d7cf0 FK |
60 | #define CONFIG_TWL4030_LED 1 |
61 | ||
62 | /* Board NAND Info */ | |
c35d7cf0 | 63 | |
c35d7cf0 FK |
64 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
65 | /* to access nand */ | |
c35d7cf0 FK |
66 | #define CONFIG_JFFS2_NAND |
67 | /* nand device jffs2 lives on */ | |
68 | #define CONFIG_JFFS2_DEV "nand0" | |
69 | /* start of jffs2 partition */ | |
70 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
71 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ | |
72 | /* partition */ | |
73 | ||
c35d7cf0 | 74 | /* BOOTP/DHCP options */ |
c35d7cf0 | 75 | #define CONFIG_BOOTP_NISDOMAIN |
c35d7cf0 | 76 | #define CONFIG_BOOTP_BOOTFILESIZE |
c35d7cf0 FK |
77 | #define CONFIG_BOOTP_DNS2 |
78 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
79 | #define CONFIG_BOOTP_NTPSERVER | |
80 | #define CONFIG_BOOTP_TIMEOFFSET | |
81 | #undef CONFIG_BOOTP_VENDOREX | |
82 | ||
83 | /* Environment information */ | |
c35d7cf0 FK |
84 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
85 | "loadaddr=0x82000000\0" \ | |
2d76da24 | 86 | "console=ttyO2,115200n8\0" \ |
f408501d | 87 | "mmcdev=0\0" \ |
c35d7cf0 FK |
88 | "vram=12M\0" \ |
89 | "dvimode=1024x768MR-16@60\0" \ | |
90 | "defaultdisplay=dvi\0" \ | |
91 | "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ | |
92 | "kernelopts=rw\0" \ | |
93 | "commonargs=" \ | |
94 | "setenv bootargs console=${console} " \ | |
95 | "vram=${vram} " \ | |
96 | "omapfb.mode=dvi:${dvimode} " \ | |
97 | "omapdss.def_disp=${defaultdisplay}\0" \ | |
98 | "mmcargs=" \ | |
99 | "run commonargs; " \ | |
100 | "setenv bootargs ${bootargs} " \ | |
101 | "root=/dev/mmcblk0p2 " \ | |
b72db208 | 102 | "rootwait " \ |
c35d7cf0 FK |
103 | "${kernelopts}\0" \ |
104 | "nandargs=" \ | |
105 | "run commonargs; " \ | |
106 | "setenv bootargs ${bootargs} " \ | |
107 | "omapfb.mode=dvi:${dvimode} " \ | |
108 | "omapdss.def_disp=${defaultdisplay} " \ | |
109 | "root=/dev/mtdblock4 " \ | |
110 | "rootfstype=jffs2 " \ | |
111 | "${kernelopts}\0" \ | |
112 | "netargs=" \ | |
113 | "run commonargs; " \ | |
114 | "setenv bootargs ${bootargs} " \ | |
115 | "root=/dev/nfs " \ | |
116 | "nfsroot=${serverip}:${rootpath},${nfsopts} " \ | |
117 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ | |
118 | "${kernelopts} " \ | |
119 | "dnsip1=${dnsip} " \ | |
120 | "dnsip2=${dnsip2}\0" \ | |
f408501d | 121 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
c35d7cf0 FK |
122 | "bootscript=echo Running bootscript from mmc ...; " \ |
123 | "source ${loadaddr}\0" \ | |
f408501d | 124 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
c35d7cf0 FK |
125 | "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ |
126 | "mmcboot=echo Booting from mmc ...; " \ | |
127 | "run mmcargs; " \ | |
128 | "bootm ${loadaddr}\0" \ | |
129 | "nandboot=echo Booting from nand ...; " \ | |
130 | "run nandargs; " \ | |
131 | "nand read ${loadaddr} 280000 400000; " \ | |
132 | "bootm ${loadaddr}\0" \ | |
133 | "netboot=echo Booting from network ...; " \ | |
134 | "dhcp ${loadaddr}; " \ | |
135 | "run netargs; " \ | |
136 | "bootm ${loadaddr}\0" \ | |
66968110 | 137 | "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ |
c35d7cf0 FK |
138 | "if run loadbootscript; then " \ |
139 | "run bootscript; " \ | |
140 | "else " \ | |
141 | "if run loaduimage; then " \ | |
142 | "run mmcboot; " \ | |
143 | "else run nandboot; " \ | |
144 | "fi; " \ | |
145 | "fi; " \ | |
146 | "else run nandboot; fi\0" | |
147 | ||
c35d7cf0 FK |
148 | #define CONFIG_BOOTCOMMAND "run autoboot" |
149 | ||
c35d7cf0 | 150 | /* Boot Argument Buffer Size */ |
c35d7cf0 FK |
151 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) |
152 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ | |
153 | 0x01000000) /* 16MB */ | |
154 | ||
c35d7cf0 | 155 | /* NAND and environment organization */ |
c35d7cf0 | 156 | |
7672d9d5 | 157 | #define CONFIG_ENV_OFFSET 0x260000 |
c35d7cf0 | 158 | |
3f6a4922 SS |
159 | /* SRAM config */ |
160 | #define CONFIG_SYS_SRAM_START 0x40200000 | |
161 | #define CONFIG_SYS_SRAM_SIZE 0x10000 | |
162 | ||
163 | /* Defines for SPL */ | |
3f6a4922 | 164 | |
a91ef4ad | 165 | #undef CONFIG_SPL_TEXT_BASE |
3f6a4922 | 166 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ |
3f6a4922 | 167 | |
3f6a4922 | 168 | /* NAND boot config */ |
c471ccb9 | 169 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
3f6a4922 SS |
170 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
171 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
172 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
173 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
174 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
175 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
176 | 10, 11, 12, 13} | |
177 | ||
178 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
179 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 180 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
3f6a4922 | 181 | |
3f6a4922 SS |
182 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
183 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 | |
184 | ||
d38bc97d | 185 | /* SPL OS boot options */ |
d38bc97d | 186 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 |
b6144dfc | 187 | |
875e4154 AB |
188 | #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR |
189 | #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR | |
190 | #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS | |
b6144dfc TR |
191 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ |
192 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ | |
193 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ | |
194 | ||
a91ef4ad | 195 | #undef CONFIG_SYS_SPL_ARGS_ADDR |
d38bc97d SS |
196 | #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) |
197 | ||
c35d7cf0 | 198 | #endif /* __CONFIG_H */ |