]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/dig297.h
imx6: move MXC_GPIO define to mx6_common.h
[people/ms/u-boot.git] / include / configs / dig297.h
CommitLineData
fb6e1f1b
LC
1/*
2 * (C) Copyright 2011 Comelit Group SpA
3 * Luca Ceresoli <luca.ceresoli@comelit.it>
4 *
5 * Based on omap3_beagle.h:
6 * (C) Copyright 2006-2008
7 * Texas Instruments.
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 *
11 * Configuration settings for the Comelit DIG297 board.
12 *
3765b3e7 13 * SPDX-License-Identifier: GPL-2.0+
fb6e1f1b
LC
14 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
30dca9dd
LC
19#include <asm/mach-types.h>
20#ifdef MACH_TYPE_OMAP3_CPS
21#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
22#else
23#define MACH_TYPE_OMAP3_CPS 2751
24#endif
25#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
c6f90e14
NM
26/* Common ARM Erratas */
27#define CONFIG_ARM_ERRATA_454179
28#define CONFIG_ARM_ERRATA_430973
29#define CONFIG_ARM_ERRATA_621766
30dca9dd 30
fb6e1f1b
LC
31/*
32 * High Level Configuration Options
33 */
fb6e1f1b 34#define CONFIG_OMAP /* in a TI OMAP core */
308252ad 35#define CONFIG_OMAP_GPIO
806d2792 36#define CONFIG_OMAP_COMMON
fb6e1f1b
LC
37
38#define CONFIG_SYS_TEXT_BASE 0x80008000
39
40#define CONFIG_SDRC /* The chip has SDRC controller */
41
42#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585 43#include <asm/arch/omap.h>
fb6e1f1b
LC
44
45/*
46 * Display CPU and Board information
47 */
48#define CONFIG_DISPLAY_CPUINFO
49#define CONFIG_DISPLAY_BOARDINFO
50
51/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
fb6e1f1b
LC
55#define CONFIG_MISC_INIT_R
56
57#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
58#define CONFIG_SETUP_MEMORY_TAGS
59#define CONFIG_INITRD_TAG
60#define CONFIG_REVISION_TAG
61
62/*
63 * Size of malloc() pool
64 */
65#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
66 /* Sector */
67#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
68
69/*
70 * Hardware drivers
71 */
72
73/*
74 * NS16550 Configuration
75 */
76#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
77
78#define CONFIG_SYS_NS16550
79#define CONFIG_SYS_NS16550_SERIAL
80#define CONFIG_SYS_NS16550_REG_SIZE (-4)
81#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
82
83/*
84 * select serial console configuration: UART3 (ttyO2)
85 */
86#define CONFIG_CONS_INDEX 3
87#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
88#define CONFIG_SERIAL3 3
89
90/* allow to overwrite serial and ethaddr */
91#define CONFIG_ENV_OVERWRITE
92#define CONFIG_BAUDRATE 115200
93#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
94 115200}
eaff60d7
TR
95#define CONFIG_GENERIC_MMC 1
96#define CONFIG_MMC 1
97#define CONFIG_OMAP_HSMMC 1
fb6e1f1b
LC
98#define CONFIG_DOS_PARTITION
99
fb6e1f1b
LC
100/* library portions to compile in */
101#define CONFIG_RBTREE
102#define CONFIG_MTD_PARTITIONS
103#define CONFIG_LZO
104
105/* commands to include */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_FAT /* FAT support */
109#define CONFIG_CMD_UBI /* UBI Support */
110#define CONFIG_CMD_UBIFS /* UBIFS Support */
111#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
112#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
113#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
114#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
115 "128k(uboot-env),3m(kernel),252m(ubi)"
116
117#define CONFIG_CMD_I2C /* I2C serial bus support */
118#define CONFIG_CMD_MMC /* MMC support */
119#define CONFIG_CMD_NAND /* NAND support */
120
121#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
122#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
123#undef CONFIG_CMD_IMI /* iminfo */
124#undef CONFIG_CMD_IMLS /* List all found images */
125#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
126#undef CONFIG_CMD_NFS /* NFS support */
127
128#define CONFIG_SYS_NO_FLASH
6789e84e
HS
129#define CONFIG_SYS_I2C
130#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
131#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
132#define CONFIG_SYS_I2C_OMAP34XX
fb6e1f1b
LC
133
134/*
135 * TWL4030
136 */
137#define CONFIG_TWL4030_POWER
138#define CONFIG_TWL4030_LED
139
140/*
141 * Board NAND Info.
142 */
143#define CONFIG_NAND_OMAP_GPMC
b80a6603 144#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
fb6e1f1b
LC
145#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
146 /* to access nand */
147#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
148 /* to access nand at */
149 /* CS0 */
fb6e1f1b
LC
150#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
151
152#if defined(CONFIG_CMD_NET)
153/*
154 * SMSC9220 Ethernet
155 */
156
fb6e1f1b
LC
157#define CONFIG_SMC911X
158#define CONFIG_SMC911X_32_BIT
159#define CONFIG_SMC911X_BASE 0x2C000000
160
161#endif /* (CONFIG_CMD_NET) */
162
163/* Environment information */
164#define CONFIG_BOOTDELAY 1
165
166#define CONFIG_EXTRA_ENV_SETTINGS \
167 "loadaddr=0x82000000\0" \
168 "console=ttyO2,115200n8\0" \
169 "mtdids=" MTDIDS_DEFAULT "\0" \
170 "mtdparts=" MTDPARTS_DEFAULT "\0" \
171 "partition=nand0,3\0"\
172 "mmcroot=/dev/mmcblk0p2 rw\0" \
173 "mmcrootfstype=ext3 rootwait\0" \
174 "nandroot=ubi0:rootfs ro\0" \
175 "nandrootfstype=ubifs\0" \
176 "nfspath=/srv/nfs\0" \
177 "tftpfilename=uImage\0" \
178 "gatewayip=0.0.0.0\0" \
179 "mmcargs=setenv bootargs console=${console} " \
180 "${mtdparts} " \
181 "root=${mmcroot} " \
182 "rootfstype=${mmcrootfstype} " \
183 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
184 "${netmask}:${hostname}::off\0" \
185 "nandargs=setenv bootargs console=${console} " \
186 "${mtdparts} " \
187 "ubi.mtd=3 " \
188 "root=${nandroot} " \
189 "rootfstype=${nandrootfstype} " \
190 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
191 "${netmask}:${hostname}::off\0" \
192 "netargs=setenv bootargs console=${console} " \
193 "${mtdparts} " \
194 "root=/dev/nfs rw " \
195 "nfsroot=${serverip}:${nfspath} " \
196 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
197 "${netmask}:${hostname}::off\0" \
198 "mmcboot=echo Booting from mmc ...; " \
199 "run mmcargs; " \
200 "bootm ${loadaddr}\0" \
201 "nandboot=echo Booting from nand ...; " \
202 "run nandargs; " \
203 "nand read ${loadaddr} 100000 300000; " \
204 "bootm ${loadaddr}\0" \
205 "netboot=echo Booting from network ...; " \
206 "run netargs; " \
207 "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
208 "bootm ${loadaddr}\0" \
209 "resetenv=nand erase e0000 20000\0"\
210
211#define CONFIG_BOOTCOMMAND \
212 "run nandboot"
213
214#define CONFIG_AUTO_COMPLETE
215/*
216 * Miscellaneous configurable options
217 */
218#define CONFIG_SYS_LONGHELP /* undef to save memory */
219#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
fb6e1f1b
LC
220#define CONFIG_SYS_PROMPT "DIG297# "
221#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
222/* Print Buffer Size */
223#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
224 sizeof(CONFIG_SYS_PROMPT) + 16)
225#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
226/* Boot Argument Buffer Size */
227#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
228
229#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
230 /* works on */
231#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
232 0x01F00000) /* 31MB */
233
234#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
235 /* load address */
236
237/*
238 * OMAP3 has 12 GP timers, they can be driven by the system clock
239 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
240 * This rate is divided by a local divisor.
241 */
242#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
243#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
fb6e1f1b 244
fb6e1f1b
LC
245/*-----------------------------------------------------------------------
246 * Physical Memory Map
247 */
248#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
249#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
fb6e1f1b
LC
250#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
251
fb6e1f1b
LC
252/*-----------------------------------------------------------------------
253 * FLASH and environment organization
254 */
255
256/* **** PISMO SUPPORT *** */
fb6e1f1b
LC
257#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
258
259#define CONFIG_SYS_FLASH_BASE boot_flash_base
260
261/* Monitor at start of flash */
262#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
263
264#define CONFIG_ENV_IS_IN_NAND
265#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
266
267#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
268#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
269#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
270
271#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
272#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
273#define CONFIG_SYS_INIT_RAM_SIZE 0x800
274#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
275 CONFIG_SYS_INIT_RAM_SIZE - \
276 GENERATED_GBL_DATA_SIZE)
277
278#endif /* __CONFIG_H */