[people/ms/u-boot.git] / include / configs / dig297.h

/*
 * (C) Copyright 2011 Comelit Group SpA
 * Luca Ceresoli <luca.ceresoli@comelit.it>
 *
 * Based on omap3_beagle.h:
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the Comelit DIG297 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/mach-types.h>
#ifdef MACH_TYPE_OMAP3_CPS
#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
#else
#define MACH_TYPE_OMAP3_CPS 2751
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		/* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON

#define CONFIG_SYS_TEXT_BASE	0x80008000

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(1024 << 10) /* UBI needs >= 512 kB */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration: UART3 (ttyO2)
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION

/* library portions to compile in */
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO

/* commands to include */
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_UBI		/* UBI Support			*/
#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands    */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:896k(uboot),"\
				"128k(uboot-env),3m(kernel),252m(ubi)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */

#if defined(CONFIG_CMD_NET)
/*
 * SMSC9220 Ethernet
 */

#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE     0x2C000000

#endif /* (CONFIG_CMD_NET) */

/* Environment information */
#define CONFIG_BOOTDELAY		1

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mtdids=" MTDIDS_DEFAULT "\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"partition=nand0,3\0"\
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ro\0" \
	"nandrootfstype=ubifs\0" \
	"nfspath=/srv/nfs\0" \
	"tftpfilename=uImage\0" \
	"gatewayip=0.0.0.0\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${mtdparts} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
			"${netmask}:${hostname}::off\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${mtdparts} " \
		"ubi.mtd=3 " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
			"${netmask}:${hostname}::off\0" \
	"netargs=setenv bootargs console=${console} " \
		"${mtdparts} " \
		"root=/dev/nfs rw " \
		"nfsroot=${serverip}:${nfspath} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
			"${netmask}:${hostname}::off\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 100000 300000; " \
		"bootm ${loadaddr}\0" \
	"netboot=echo Booting from network ...; " \
		"run netargs; " \
		"tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
		"bootm ${loadaddr}\0" \
	"resetenv=nand erase e0000 20000\0"\

#define CONFIG_BOOTCOMMAND \
	"run nandboot"

#define CONFIG_AUTO_COMPLETE
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x0E0000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#endif /* __CONFIG_H */
Commit	Line	Data
fb6e1f1b LC	1	/*
	2	* (C) Copyright 2011 Comelit Group SpA
	3	* Luca Ceresoli <luca.ceresoli@comelit.it>
	4	*
	5	* Based on omap3_beagle.h:
	6	* (C) Copyright 2006-2008
	7	* Texas Instruments.
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Syed Mohammed Khasim <x0khasim@ti.com>
	10	*
	11	* Configuration settings for the Comelit DIG297 board.
	12	*
3765b3e7	13	* SPDX-License-Identifier: GPL-2.0+
fb6e1f1b LC	14	*/
	15
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
30dca9dd LC	19	#include <asm/mach-types.h>
	20	#ifdef MACH_TYPE_OMAP3_CPS
	21	#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
	22	#else
	23	#define MACH_TYPE_OMAP3_CPS 2751
	24	#endif
	25	#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
c6f90e14 NM	26	/* Common ARM Erratas */
	27	#define CONFIG_ARM_ERRATA_454179
	28	#define CONFIG_ARM_ERRATA_430973
	29	#define CONFIG_ARM_ERRATA_621766
30dca9dd	30
fb6e1f1b LC	31	/*
	32	* High Level Configuration Options
	33	*/
fb6e1f1b	34	#define CONFIG_OMAP /* in a TI OMAP core */
308252ad	35	#define CONFIG_OMAP_GPIO
806d2792	36	#define CONFIG_OMAP_COMMON
fb6e1f1b LC	37
	38	#define CONFIG_SYS_TEXT_BASE 0x80008000
	39
	40	#define CONFIG_SDRC /* The chip has SDRC controller */
	41
	42	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	43	#include <asm/arch/omap.h>
fb6e1f1b LC	44
	45	/*
	46	* Display CPU and Board information
	47	*/
	48	#define CONFIG_DISPLAY_CPUINFO
	49	#define CONFIG_DISPLAY_BOARDINFO
	50
	51	/* Clock Defines */
	52	#define V_OSCK 26000000 /* Clock output from T2 */
	53	#define V_SCLK (V_OSCK >> 1)
	54
fb6e1f1b LC	55	#define CONFIG_MISC_INIT_R
	56
	57	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	58	#define CONFIG_SETUP_MEMORY_TAGS
	59	#define CONFIG_INITRD_TAG
	60	#define CONFIG_REVISION_TAG
	61
	62	/*
	63	* Size of malloc() pool
	64	*/
	65	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
	66	/* Sector */
	67	#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
	68
	69	/*
	70	* Hardware drivers
	71	*/
	72
	73	/*
	74	* NS16550 Configuration
	75	*/
	76	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	77
	78	#define CONFIG_SYS_NS16550
	79	#define CONFIG_SYS_NS16550_SERIAL
	80	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	81	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	82
	83	/*
	84	* select serial console configuration: UART3 (ttyO2)
	85	*/
	86	#define CONFIG_CONS_INDEX 3
	87	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	88	#define CONFIG_SERIAL3 3
	89
	90	/* allow to overwrite serial and ethaddr */
	91	#define CONFIG_ENV_OVERWRITE
	92	#define CONFIG_BAUDRATE 115200
	93	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	94	115200}
eaff60d7 TR	95	#define CONFIG_GENERIC_MMC 1
	96	#define CONFIG_MMC 1
	97	#define CONFIG_OMAP_HSMMC 1
fb6e1f1b LC	98	#define CONFIG_DOS_PARTITION
fb6e1f1b LC	99
fb6e1f1b LC	100	/* library portions to compile in */
	101	#define CONFIG_RBTREE
	102	#define CONFIG_MTD_PARTITIONS
	103	#define CONFIG_LZO
	104
	105	/* commands to include */
fb6e1f1b LC	106	#define CONFIG_CMD_FAT /* FAT support */
	107	#define CONFIG_CMD_UBI /* UBI Support */
	108	#define CONFIG_CMD_UBIFS /* UBIFS Support */
	109	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	110	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	111	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	112	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
	113	"128k(uboot-env),3m(kernel),252m(ubi)"
	114
	115	#define CONFIG_CMD_I2C /* I2C serial bus support */
	116	#define CONFIG_CMD_MMC /* MMC support */
	117	#define CONFIG_CMD_NAND /* NAND support */
	118
fb6e1f1b	119	#define CONFIG_SYS_NO_FLASH
6789e84e HS	120	#define CONFIG_SYS_I2C
	121	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	122	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	123	#define CONFIG_SYS_I2C_OMAP34XX
fb6e1f1b LC	124
	125	/*
	126	* TWL4030
	127	*/
	128	#define CONFIG_TWL4030_POWER
	129	#define CONFIG_TWL4030_LED
	130
	131	/*
	132	* Board NAND Info.
	133	*/
	134	#define CONFIG_NAND_OMAP_GPMC
55f1b39f	135	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
fb6e1f1b LC	136	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	137	/* to access nand */
	138	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	139	/* to access nand at */
	140	/* CS0 */
fb6e1f1b LC	141	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	142
	143	#if defined(CONFIG_CMD_NET)
	144	/*
	145	* SMSC9220 Ethernet
	146	*/
	147
fb6e1f1b LC	148	#define CONFIG_SMC911X
	149	#define CONFIG_SMC911X_32_BIT
	150	#define CONFIG_SMC911X_BASE 0x2C000000
	151
	152	#endif /* (CONFIG_CMD_NET) */
	153
	154	/* Environment information */
	155	#define CONFIG_BOOTDELAY 1
	156
	157	#define CONFIG_EXTRA_ENV_SETTINGS \
	158	"loadaddr=0x82000000\0" \
	159	"console=ttyO2,115200n8\0" \
	160	"mtdids=" MTDIDS_DEFAULT "\0" \
	161	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	162	"partition=nand0,3\0"\
	163	"mmcroot=/dev/mmcblk0p2 rw\0" \
	164	"mmcrootfstype=ext3 rootwait\0" \
	165	"nandroot=ubi0:rootfs ro\0" \
	166	"nandrootfstype=ubifs\0" \
	167	"nfspath=/srv/nfs\0" \
	168	"tftpfilename=uImage\0" \
	169	"gatewayip=0.0.0.0\0" \
	170	"mmcargs=setenv bootargs console=${console} " \
	171	"${mtdparts} " \
	172	"root=${mmcroot} " \
	173	"rootfstype=${mmcrootfstype} " \
	174	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	175	"${netmask}:${hostname}::off\0" \
	176	"nandargs=setenv bootargs console=${console} " \
	177	"${mtdparts} " \
	178	"ubi.mtd=3 " \
	179	"root=${nandroot} " \
	180	"rootfstype=${nandrootfstype} " \
	181	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	182	"${netmask}:${hostname}::off\0" \
	183	"netargs=setenv bootargs console=${console} " \
	184	"${mtdparts} " \
	185	"root=/dev/nfs rw " \
	186	"nfsroot=${serverip}:${nfspath} " \
	187	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	188	"${netmask}:${hostname}::off\0" \
	189	"mmcboot=echo Booting from mmc ...; " \
	190	"run mmcargs; " \
	191	"bootm ${loadaddr}\0" \
	192	"nandboot=echo Booting from nand ...; " \
	193	"run nandargs; " \
	194	"nand read ${loadaddr} 100000 300000; " \
	195	"bootm ${loadaddr}\0" \
	196	"netboot=echo Booting from network ...; " \
	197	"run netargs; " \
	198	"tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
	199	"bootm ${loadaddr}\0" \
	200	"resetenv=nand erase e0000 20000\0"\
	201
	202	#define CONFIG_BOOTCOMMAND \
	203	"run nandboot"
	204
	205	#define CONFIG_AUTO_COMPLETE
	206	/*
	207	* Miscellaneous configurable options
	208	*/
	209	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	210	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
fb6e1f1b LC	211	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	212	/* Print Buffer Size */
	213	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	214	sizeof(CONFIG_SYS_PROMPT) + 16)
	215	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	216	/* Boot Argument Buffer Size */
	217	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	218
	219	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	220	/* works on */
	221	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	222	0x01F00000) /* 31MB */
	223
	224	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	225	/* load address */
	226
	227	/*
	228	* OMAP3 has 12 GP timers, they can be driven by the system clock
	229	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	230	* This rate is divided by a local divisor.
	231	*/
	232	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	233	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
fb6e1f1b	234
fb6e1f1b LC	235	/*-----------------------------------------------------------------------
	236	* Physical Memory Map
	237	*/
	238	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	239	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
fb6e1f1b LC	240	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
fb6e1f1b LC	241
fb6e1f1b LC	242	/*-----------------------------------------------------------------------
	243	* FLASH and environment organization
	244	*/
	245
	246	/* ** PISMO SUPPORT * */
fb6e1f1b LC	247	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	248
	249	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	250
	251	/* Monitor at start of flash */
	252	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	253
	254	#define CONFIG_ENV_IS_IN_NAND
	255	#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
	256
	257	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	258	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	259	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	260
	261	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	262	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	263	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	264	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	265	CONFIG_SYS_INIT_RAM_SIZE - \
	266	GENERATED_GBL_DATA_SIZE)
	267
	268	#endif /* __CONFIG_H */