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b209a114 DE |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b209a114 DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ | |
b209a114 DE |
12 | #define CONFIG_DLVISION 1 /* on a Neo board */ |
13 | ||
2ae18241 WD |
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
15 | ||
b209a114 DE |
16 | /* |
17 | * Include common defines/options for all AMCC eval boards | |
18 | */ | |
19 | #define CONFIG_HOSTNAME dlvision | |
b209a114 DE |
20 | #include "amcc-common.h" |
21 | ||
b209a114 DE |
22 | #define CONFIG_MISC_INIT_R /* call misc_init_r */ |
23 | ||
24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
25 | ||
26 | /* | |
27 | * Configure PLL | |
28 | */ | |
29 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
30 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
31 | ||
b209a114 DE |
32 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
33 | ||
34 | /* | |
35 | * Default environment variables | |
36 | */ | |
37 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
38 | CONFIG_AMCC_DEF_ENV \ | |
39 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
40 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
41 | "kernel_addr=fc000000\0" \ | |
42 | "fdt_addr=fc1e0000\0" \ | |
43 | "ramdisk_addr=fc200000\0" \ | |
44 | "" | |
45 | ||
46 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
47 | #define CONFIG_HAS_ETH0 | |
48 | #define CONFIG_HAS_ETH1 | |
49 | #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ | |
50 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
51 | ||
52 | /* | |
53 | * Commands additional to the ones defined in amcc-common.h | |
54 | */ | |
b209a114 DE |
55 | |
56 | /* | |
57 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
58 | */ | |
59 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
60 | ||
61 | /* SDRAM timings used in datasheet */ | |
62 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
63 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
64 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ | |
65 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
66 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
67 | ||
68 | /* | |
69 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
70 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
71 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. | |
72 | * The Linux BASE_BAUD define should match this configuration. | |
73 | * baseBaud = cpuClock/(uartDivisor*16) | |
74 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
75 | * set Linux BASE_BAUD to 403200. | |
76 | */ | |
550650dd | 77 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
b209a114 DE |
78 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
79 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
80 | #define CONFIG_SYS_BASE_BAUD 691200 | |
81 | ||
82 | /* | |
83 | * I2C stuff | |
84 | */ | |
880540de | 85 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
b209a114 DE |
86 | |
87 | /* | |
88 | * FLASH organization | |
89 | */ | |
90 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
91 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
92 | ||
93 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
94 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
95 | ||
96 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
97 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ | |
98 | ||
99 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ | |
100 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ | |
101 | ||
102 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ | |
b209a114 DE |
103 | |
104 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ | |
105 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ | |
106 | ||
107 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
108 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
109 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) | |
110 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
111 | ||
112 | /* Address and size of Redundant Environment Sector */ | |
113 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
114 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
115 | #endif | |
116 | ||
117 | /* | |
118 | * PPC405 GPIO Configuration | |
119 | */ | |
120 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ | |
121 | { \ | |
122 | /* GPIO Core 0 */ \ | |
123 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
124 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
125 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
126 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
127 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
128 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
129 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
130 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ | |
131 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
132 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
133 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
134 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
135 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
136 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
137 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
138 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
139 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
140 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
141 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
142 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
143 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
144 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
145 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
146 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
147 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
148 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
149 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
150 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
151 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
152 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
153 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
154 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
155 | } \ | |
156 | } | |
157 | ||
158 | /* | |
159 | * Definitions for initial stack pointer and data area (in data cache) | |
160 | */ | |
161 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
162 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
163 | ||
164 | /* On Chip Memory location */ | |
165 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
166 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
167 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ | |
553f0982 | 168 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */ |
b209a114 | 169 | |
b209a114 | 170 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 171 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
b209a114 DE |
172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
173 | ||
174 | /* | |
175 | * External Bus Controller (EBC) Setup | |
176 | */ | |
177 | ||
178 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
179 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 | |
180 | /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ | |
181 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 | |
182 | ||
183 | /* Memory Bank 1 (NVRAM) initializatio */ | |
184 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 | |
185 | /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ | |
186 | #define CONFIG_SYS_EBC_PB1CR 0xFB858000 | |
187 | ||
188 | /* Memory Bank 2 (UART) initialization */ | |
189 | #define CONFIG_UART_BASE 0x7f100000 | |
190 | #define CONFIG_SYS_EBC_PB2AP 0x92015480 | |
191 | /* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */ | |
192 | #define CONFIG_SYS_EBC_PB2CR 0x7f118000 | |
193 | ||
194 | /* Memory Bank 3 (Latches) initialization */ | |
195 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 | |
196 | #define CONFIG_SYS_EBC_PB3AP 0x92015480 | |
197 | /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ | |
198 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 | |
199 | ||
200 | #endif /* __CONFIG_H */ |