[thirdparty/u-boot.git] / include / configs / ds414.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 */

#ifndef _CONFIG_SYNOLOGY_DS414_H
#define _CONFIG_SYNOLOGY_DS414_H

/*
 * High Level Configuration Options (easy to change)
 */

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET		0x7E0000   /* RedBoot config partition in DTS */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII

/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_SCAN_SHOW
#endif

/* USB/EHCI/XHCI configuration */

#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

/* FIXME: broken XHCI support
 * Below defines should enable support for the two rear USB3 ports. Sadly, this
 * does not work because:
 * - xhci-pci seems to not support DM_USB, so with that enabled it is not
 *   found.
 * - USB init fails, controller does not respond in time */

#if !defined(CONFIG_USB_XHCI_HCD)
#define CONFIG_EHCI_IS_TDI
#endif

/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x24000

/* DS414 bus width is 32bits */
#define CONFIG_DDR_32BIT

/* Default Environment */
#define CONFIG_BOOTCOMMAND	"sf read ${loadaddr} 0xd0000 0x700000; bootm"
#define CONFIG_LOADADDR		0x80000

#endif /* _CONFIG_SYNOLOGY_DS414_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
aefb8f4c PS	2	/*
aefb8f4c PS	3	* Copyright (C) 2014 Stefan Roese <sr@denx.de>
aefb8f4c PS	4	*/
	5
	6	#ifndef _CONFIG_SYNOLOGY_DS414_H
	7	#define _CONFIG_SYNOLOGY_DS414_H
	8
	9	/*
	10	* High Level Configuration Options (easy to change)
	11	*/
aefb8f4c PS	12
	13	/*
	14	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	15	* for DDR ECC byte filling in the SPL before loading the main
	16	* U-Boot into it.
	17	*/
aefb8f4c PS	18	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	19
	20	/*
	21	* Commands configuration
	22	*/
aefb8f4c PS	23
	24	/* I2C */
	25	#define CONFIG_SYS_I2C
	26	#define CONFIG_SYS_I2C_MVTWSI
	27	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
	28	#define CONFIG_SYS_I2C_SLAVE 0x0
	29	#define CONFIG_SYS_I2C_SPEED 100000
	30
aefb8f4c	31	/* Environment in SPI NOR flash */
aefb8f4c PS	32	#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
	33	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	34	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	35
aefb8f4c PS	36	#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
aefb8f4c PS	37
aefb8f4c PS	38	/* PCIe support */
aefb8f4c PS	39	#ifndef CONFIG_SPL_BUILD
aefb8f4c PS	40	#define CONFIG_PCI_SCAN_SHOW
	41	#endif
	42
	43	/* USB/EHCI/XHCI configuration */
	44
aefb8f4c PS	45	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	46
	47	/* FIXME: broken XHCI support
	48	* Below defines should enable support for the two rear USB3 ports. Sadly, this
	49	* does not work because:
	50	* - xhci-pci seems to not support DM_USB, so with that enabled it is not
	51	* found.
	52	* - USB init fails, controller does not respond in time */
aefb8f4c	53
0a8cc1a3	54	#if !defined(CONFIG_USB_XHCI_HCD)
aefb8f4c PS	55	#define CONFIG_EHCI_IS_TDI
	56	#endif
	57
	58	/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
aefb8f4c PS	59
	60	/*
	61	* mv-common.h should be defined after CMD configs since it used them
	62	* to enable certain macros
	63	*/
	64	#include "mv-common.h"
	65
	66	/*
	67	* Memory layout while starting into the bin_hdr via the
	68	* BootROM:
	69	*
	70	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	71	* 0x4000.4030 bin_hdr start address
	72	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	73	* 0x4007.fffc BootROM stack top
	74	*
	75	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	76	* L2 cache thus cannot be used.
	77	*/
	78
	79	/* SPL */
	80	/* Defines for SPL */
aefb8f4c PS	81	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	82
	83	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	84	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	85
	86	#ifdef CONFIG_SPL_BUILD
	87	#define CONFIG_SYS_MALLOC_SIMPLE
	88	#endif
	89
	90	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	91	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	92
aefb8f4c	93	/* SPL related SPI defines */
aefb8f4c PS	94	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
	95
	96	/* DS414 bus width is 32bits */
	97	#define CONFIG_DDR_32BIT
	98
aefb8f4c PS	99	/* Default Environment */
aefb8f4c PS	100	#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
aefb8f4c	101	#define CONFIG_LOADADDR 0x80000
aefb8f4c PS	102
aefb8f4c PS	103	#endif /* _CONFIG_SYNOLOGY_DS414_H */