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80885a9d WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* ------------------------------------------------------------------------- */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC824X 1 | |
39 | /* #define CONFIG_MPC8240 1 */ | |
40 | #define CONFIG_MPC8245 1 | |
41 | #define CONFIG_EXALION 1 | |
42 | ||
2ae18241 WD |
43 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
44 | ||
80885a9d WD |
45 | #if defined (CONFIG_MPC8240) |
46 | /* #warning ---------- eXalion with MPC8240 --------------- */ | |
47 | #elif defined (CONFIG_MPC8245) | |
48 | /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ | |
49 | #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) | |
50 | #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) | |
51 | #else | |
52 | #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
53 | #endif | |
54 | /* older kernels need clock in MHz newer in Hz */ | |
132ba5fd | 55 | /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ |
80885a9d WD |
56 | #undef CONFIG_CLOCKS_IN_MHZ |
57 | ||
58 | #define CONFIG_BOOTDELAY 10 | |
59 | ||
60 | ||
132ba5fd | 61 | /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ |
80885a9d | 62 | |
80ff4f99 JL |
63 | /* |
64 | * BOOTP options | |
65 | */ | |
66 | #define CONFIG_BOOTP_BOOTFILESIZE | |
67 | #define CONFIG_BOOTP_BOOTPATH | |
68 | #define CONFIG_BOOTP_GATEWAY | |
69 | #define CONFIG_BOOTP_HOSTNAME | |
70 | ||
71 | ||
1bec3d30 JL |
72 | /* |
73 | * Command line configuration. | |
74 | */ | |
75 | #include <config_cmd_default.h> | |
80885a9d | 76 | |
1bec3d30 JL |
77 | #define CONFIG_CMD_FLASH |
78 | #define CONFIG_CMD_SDRAM | |
79 | #define CONFIG_CMD_I2C | |
80 | #define CONFIG_CMD_IDE | |
81 | #define CONFIG_CMD_FAT | |
bdab39d3 | 82 | #define CONFIG_CMD_SAVEENV |
1bec3d30 | 83 | #define CONFIG_CMD_PCI |
80885a9d WD |
84 | |
85 | ||
86 | /*----------------------------------------------------------------------- | |
87 | * Miscellaneous configurable options | |
88 | */ | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
90 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
91 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
92 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
93 | #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ | |
94 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
95 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
80885a9d WD |
96 | #define CONFIG_MISC_INIT_R 1 |
97 | ||
98 | /*----------------------------------------------------------------------- | |
99 | * Start addresses for the final memory configuration | |
100 | * (Set up by the startup code) | |
6d0f6bcf | 101 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
80885a9d | 102 | */ |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
104 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ | |
80885a9d WD |
105 | /* return real value. */ |
106 | ||
6d0f6bcf | 107 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
80885a9d | 108 | |
6d0f6bcf JCPV |
109 | #undef CONFIG_SYS_RAMBOOT |
110 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
14d0a02a | 111 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
80885a9d WD |
112 | |
113 | /*----------------------------------------------------------------------- | |
114 | * Definitions for initial stack pointer and data area | |
115 | */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_INIT_DATA_SIZE 128 |
80885a9d | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 WD |
119 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
120 | #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) | |
80885a9d | 121 | |
25ddd1fb | 122 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 123 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
80885a9d WD |
124 | |
125 | ||
126 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_BASE 0xFFE00000 |
128 | #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ | |
80885a9d | 129 | #elif defined (CONFIG_MPC8245) |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
131 | #define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ | |
80885a9d WD |
132 | #else |
133 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
134 | #endif | |
135 | ||
5a1aceb0 | 136 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
137 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ |
138 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ | |
139 | #define CONFIG_ENV_ADDR 0xFFFC0000 | |
140 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ | |
80885a9d | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
80885a9d | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ |
145 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ | |
146 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
80885a9d | 147 | |
6d0f6bcf | 148 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
80885a9d | 149 | |
6d0f6bcf JCPV |
150 | /* #define CONFIG_SYS_ISA_MEM 0xFD000000 */ |
151 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
80885a9d WD |
152 | |
153 | /*----------------------------------------------------------------------- | |
154 | * FLASH organization | |
155 | */ | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
157 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ | |
80885a9d | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
160 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
80885a9d | 161 | |
6d0f6bcf | 162 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE |
80885a9d WD |
163 | #define FLASH_BASE1_PRELIM 0 |
164 | ||
165 | ||
166 | /*----------------------------------------------------------------------- | |
167 | * FLASH and environment organization | |
168 | */ | |
169 | ||
6d0f6bcf | 170 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 171 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
173 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
174 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
175 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
176 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
80885a9d WD |
177 | |
178 | ||
179 | /*----------------------------------------------------------------------- | |
180 | * PCI stuff | |
181 | */ | |
182 | #define CONFIG_PCI 1 /* include pci support */ | |
842033e6 | 183 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
80885a9d WD |
184 | #undef CONFIG_PCI_PNP |
185 | ||
80885a9d WD |
186 | |
187 | #define CONFIG_EEPRO100 1 | |
188 | ||
189 | #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ | |
190 | #define PCI_ENET0_IOADDR 0x80000000 | |
191 | #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ | |
192 | #define PCI_ENET1_IOADDR 0x81000000 | |
193 | #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ | |
194 | #define PCI_ENET2_IOADDR 0x82000000 | |
195 | #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ | |
196 | #define PCI_ENET3_IOADDR 0x83000000 | |
197 | ||
198 | /*----------------------------------------------------------------------- | |
199 | * NS16550 Configuration | |
200 | */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_NS16550 1 |
202 | #define CONFIG_SYS_NS16550_SERIAL 1 | |
80885a9d WD |
203 | |
204 | #define CONFIG_CONS_INDEX 1 | |
205 | #define CONFIG_BAUDRATE 38400 | |
206 | ||
6d0f6bcf | 207 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
80885a9d WD |
208 | |
209 | #if (CONFIG_CONS_INDEX == 1) | |
6d0f6bcf | 210 | #define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */ |
80885a9d | 211 | #else |
6d0f6bcf | 212 | #define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) |
80885a9d WD |
213 | #endif |
214 | ||
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8) |
216 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) | |
217 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
80885a9d WD |
218 | |
219 | /*----------------------------------------------------------------------- | |
220 | * select i2c support configuration | |
221 | * | |
222 | * Supported configurations are {none, software, hardware} drivers. | |
223 | * If the software driver is chosen, there are some additional | |
224 | * configuration items that the driver uses to drive the port pins. | |
225 | */ | |
226 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
ea818dbb | 227 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
229 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
80885a9d WD |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * Low Level Configuration Settings | |
233 | * (address mappings, register initial values, etc.) | |
234 | * You should know what you are doing if you make changes here. | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_HZ 1000 |
80885a9d WD |
237 | |
238 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
239 | #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ | |
240 | ||
132ba5fd | 241 | /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ |
80885a9d WD |
242 | |
243 | #if defined (CONFIG_MPC8245) | |
244 | /* Bit-field values for PMCR2. */ | |
245 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ |
247 | #define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ | |
80885a9d WD |
248 | #endif |
249 | ||
250 | /* Bit-field values for MIOCR1. */ | |
251 | #if !defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 252 | #define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ |
80885a9d WD |
253 | #endif |
254 | /* Bit-field values for MIOCR2. */ | |
6d0f6bcf | 255 | #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ |
80885a9d WD |
256 | /* - note bottom 3 bits MUST be 0 */ |
257 | #endif | |
258 | ||
259 | /* Bit-field values for MCCR1. */ | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
261 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
80885a9d WD |
262 | |
263 | /* Bit-field values for MCCR2. */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ |
80885a9d | 265 | #if defined (CONFIG_133MHZ_DRAM) |
6d0f6bcf | 266 | #define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */ |
80885a9d | 267 | #else /* refresh cycles */ |
6d0f6bcf | 268 | #define CONFIG_SYS_REFINT 750 |
80885a9d WD |
269 | #endif |
270 | ||
271 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ | |
272 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 273 | #define CONFIG_SYS_BSTOPRE 1023 |
80885a9d | 274 | #else |
6d0f6bcf | 275 | #define CONFIG_SYS_BSTOPRE 250 |
80885a9d WD |
276 | #endif |
277 | ||
278 | /* Bit-field values for MCCR3. */ | |
279 | /* the following are for SDRAM only */ | |
280 | ||
281 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 282 | #define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */ |
80885a9d | 283 | #else |
6d0f6bcf | 284 | #define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */ |
80885a9d WD |
285 | #endif |
286 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf | 287 | #define CONFIG_SYS_RDLAT 2 /* data latency from read command */ |
80885a9d WD |
288 | #endif |
289 | ||
290 | /* Bit-field values for MCCR4. */ | |
291 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ |
293 | #define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */ | |
294 | #define CONFIG_SYS_ACTORW 5 /* Activate to R/W */ | |
295 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
80885a9d WD |
296 | #else |
297 | #if 0 | |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
299 | #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ | |
300 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
301 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ | |
80885a9d | 302 | #endif |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
304 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
305 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
306 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
80885a9d | 307 | #endif |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ |
309 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ | |
310 | #define CONFIG_SYS_REGDIMM 0 | |
80885a9d | 311 | #if defined (CONFIG_MPC8240) |
6d0f6bcf | 312 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0 |
80885a9d | 313 | #elif defined (CONFIG_MPC8245) |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
315 | #define CONFIG_SYS_EXTROM 0 | |
80885a9d WD |
316 | #else |
317 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
318 | #endif | |
319 | ||
320 | ||
321 | /*----------------------------------------------------------------------- | |
322 | memory bank settings | |
323 | * only bits 20-29 are actually used from these vales to set the | |
324 | * start/end address the upper two bits will be 0, and the lower 20 | |
325 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
326 | * end address | |
327 | */ | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_BANK0_START 0x00000000 |
329 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
330 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
331 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
332 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
333 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
334 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
335 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
336 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
337 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
338 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
339 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
340 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
341 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
342 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
343 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
344 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
345 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
346 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
347 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
348 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
349 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
350 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
351 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
80885a9d WD |
352 | |
353 | /*----------------------------------------------------------------------- | |
354 | * Memory bank enable bitmask, specifying which of the banks defined above | |
355 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
356 | */ | |
6d0f6bcf | 357 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
80885a9d WD |
358 | |
359 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf | 360 | #define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */ |
80885a9d WD |
361 | /* see 8240 book for bit definitions */ |
362 | #elif defined (CONFIG_MPC8245) | |
363 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 364 | #define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */ |
80885a9d | 365 | #else |
6d0f6bcf | 366 | #define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */ |
80885a9d WD |
367 | #endif |
368 | #else | |
369 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
370 | #endif | |
371 | ||
6d0f6bcf | 372 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
80885a9d WD |
373 | /* currently accessed page in memory */ |
374 | /* see 8240 book for details */ | |
375 | ||
376 | /*----------------------------------------------------------------------- | |
377 | * Block Address Translation (BAT) register settings. | |
378 | */ | |
379 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
381 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d WD |
382 | |
383 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
385 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
80885a9d WD |
386 | |
387 | /* PCI memory */ | |
6d0f6bcf JCPV |
388 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
389 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d WD |
390 | |
391 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
393 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d | 394 | |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
396 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
397 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
398 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
399 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
400 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
401 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
402 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
80885a9d WD |
403 | |
404 | ||
405 | /*----------------------------------------------------------------------- | |
406 | * Cache Configuration | |
407 | */ | |
6d0f6bcf | 408 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
1bec3d30 | 409 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 410 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
80885a9d WD |
411 | #endif |
412 | ||
80885a9d WD |
413 | /* values according to the manual */ |
414 | #define CONFIG_DRAM_50MHZ 1 | |
415 | #define CONFIG_SDRAM_50MHZ | |
416 | ||
417 | #undef NR_8259_INTS | |
418 | #define NR_8259_INTS 1 | |
419 | ||
420 | /*----------------------------------------------------------------------- | |
421 | * IDE/ATA stuff | |
422 | */ | |
6d0f6bcf JCPV |
423 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ |
424 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ | |
80885a9d | 425 | |
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */ |
427 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
428 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
429 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
430 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
431 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
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432 | |
433 | #define CONFIG_ATAPI | |
434 | ||
435 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
436 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
437 | #undef CONFIG_IDE_RESET /* reset for ide supported... */ | |
438 | #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
439 | ||
440 | /*----------------------------------------------------------------------- | |
441 | * DISK Partition support | |
442 | */ | |
443 | #define CONFIG_DOS_PARTITION | |
444 | ||
445 | /*----------------------------------------------------------------------- | |
446 | * For booting Linux, the board info and command line data | |
447 | * have to be in the first 8 MB of memory, since this is | |
448 | * the maximum mapped by the Linux kernel during initialization. | |
449 | */ | |
6d0f6bcf | 450 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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451 | |
452 | #endif /* __CONFIG_H */ |