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Commit | Line | Data |
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80885a9d WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
80885a9d WD |
6 | */ |
7 | ||
8 | /* ------------------------------------------------------------------------- */ | |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | ||
22 | #define CONFIG_MPC824X 1 | |
23 | /* #define CONFIG_MPC8240 1 */ | |
24 | #define CONFIG_MPC8245 1 | |
25 | #define CONFIG_EXALION 1 | |
26 | ||
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
28 | ||
80885a9d WD |
29 | #if defined (CONFIG_MPC8240) |
30 | /* #warning ---------- eXalion with MPC8240 --------------- */ | |
31 | #elif defined (CONFIG_MPC8245) | |
32 | /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ | |
33 | #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) | |
34 | #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) | |
35 | #else | |
36 | #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
37 | #endif | |
38 | /* older kernels need clock in MHz newer in Hz */ | |
132ba5fd | 39 | /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ |
80885a9d WD |
40 | #undef CONFIG_CLOCKS_IN_MHZ |
41 | ||
42 | #define CONFIG_BOOTDELAY 10 | |
43 | ||
44 | ||
132ba5fd | 45 | /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ |
80885a9d | 46 | |
80ff4f99 JL |
47 | /* |
48 | * BOOTP options | |
49 | */ | |
50 | #define CONFIG_BOOTP_BOOTFILESIZE | |
51 | #define CONFIG_BOOTP_BOOTPATH | |
52 | #define CONFIG_BOOTP_GATEWAY | |
53 | #define CONFIG_BOOTP_HOSTNAME | |
54 | ||
55 | ||
1bec3d30 JL |
56 | /* |
57 | * Command line configuration. | |
58 | */ | |
59 | #include <config_cmd_default.h> | |
80885a9d | 60 | |
1bec3d30 JL |
61 | #define CONFIG_CMD_FLASH |
62 | #define CONFIG_CMD_SDRAM | |
63 | #define CONFIG_CMD_I2C | |
64 | #define CONFIG_CMD_IDE | |
65 | #define CONFIG_CMD_FAT | |
bdab39d3 | 66 | #define CONFIG_CMD_SAVEENV |
1bec3d30 | 67 | #define CONFIG_CMD_PCI |
80885a9d WD |
68 | |
69 | ||
70 | /*----------------------------------------------------------------------- | |
71 | * Miscellaneous configurable options | |
72 | */ | |
6d0f6bcf | 73 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
75 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
76 | #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ | |
77 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
78 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
80885a9d WD |
79 | #define CONFIG_MISC_INIT_R 1 |
80 | ||
81 | /*----------------------------------------------------------------------- | |
82 | * Start addresses for the final memory configuration | |
83 | * (Set up by the startup code) | |
6d0f6bcf | 84 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
80885a9d | 85 | */ |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
87 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ | |
80885a9d WD |
88 | /* return real value. */ |
89 | ||
6d0f6bcf | 90 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
80885a9d | 91 | |
6d0f6bcf JCPV |
92 | #undef CONFIG_SYS_RAMBOOT |
93 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
14d0a02a | 94 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
80885a9d WD |
95 | |
96 | /*----------------------------------------------------------------------- | |
97 | * Definitions for initial stack pointer and data area | |
98 | */ | |
6d0f6bcf | 99 | #define CONFIG_SYS_INIT_DATA_SIZE 128 |
80885a9d | 100 | |
6d0f6bcf | 101 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 WD |
102 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
103 | #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) | |
80885a9d | 104 | |
25ddd1fb | 105 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 106 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
80885a9d WD |
107 | |
108 | ||
109 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_FLASH_BASE 0xFFE00000 |
111 | #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ | |
80885a9d | 112 | #elif defined (CONFIG_MPC8245) |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
114 | #define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ | |
80885a9d WD |
115 | #else |
116 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
117 | #endif | |
118 | ||
5a1aceb0 | 119 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 120 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ |
1bce2aeb | 121 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */ |
0e8d1586 JCPV |
122 | #define CONFIG_ENV_ADDR 0xFFFC0000 |
123 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ | |
80885a9d | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
80885a9d | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ |
128 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ | |
129 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
80885a9d | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
80885a9d | 132 | |
6d0f6bcf JCPV |
133 | /* #define CONFIG_SYS_ISA_MEM 0xFD000000 */ |
134 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
80885a9d WD |
135 | |
136 | /*----------------------------------------------------------------------- | |
137 | * FLASH organization | |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
140 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ | |
80885a9d | 141 | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
143 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
80885a9d | 144 | |
6d0f6bcf | 145 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE |
80885a9d WD |
146 | #define FLASH_BASE1_PRELIM 0 |
147 | ||
148 | ||
149 | /*----------------------------------------------------------------------- | |
150 | * FLASH and environment organization | |
151 | */ | |
152 | ||
6d0f6bcf | 153 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 154 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
156 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
157 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
158 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
159 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
80885a9d WD |
160 | |
161 | ||
162 | /*----------------------------------------------------------------------- | |
163 | * PCI stuff | |
164 | */ | |
165 | #define CONFIG_PCI 1 /* include pci support */ | |
842033e6 | 166 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
80885a9d WD |
167 | #undef CONFIG_PCI_PNP |
168 | ||
80885a9d WD |
169 | |
170 | #define CONFIG_EEPRO100 1 | |
171 | ||
172 | #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ | |
173 | #define PCI_ENET0_IOADDR 0x80000000 | |
174 | #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ | |
175 | #define PCI_ENET1_IOADDR 0x81000000 | |
176 | #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ | |
177 | #define PCI_ENET2_IOADDR 0x82000000 | |
178 | #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ | |
179 | #define PCI_ENET3_IOADDR 0x83000000 | |
180 | ||
181 | /*----------------------------------------------------------------------- | |
182 | * NS16550 Configuration | |
183 | */ | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_NS16550 1 |
185 | #define CONFIG_SYS_NS16550_SERIAL 1 | |
80885a9d WD |
186 | |
187 | #define CONFIG_CONS_INDEX 1 | |
188 | #define CONFIG_BAUDRATE 38400 | |
189 | ||
6d0f6bcf | 190 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
80885a9d WD |
191 | |
192 | #if (CONFIG_CONS_INDEX == 1) | |
6d0f6bcf | 193 | #define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */ |
80885a9d | 194 | #else |
6d0f6bcf | 195 | #define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) |
80885a9d WD |
196 | #endif |
197 | ||
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8) |
199 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) | |
200 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
80885a9d WD |
201 | |
202 | /*----------------------------------------------------------------------- | |
203 | * select i2c support configuration | |
204 | * | |
205 | * Supported configurations are {none, software, hardware} drivers. | |
206 | * If the software driver is chosen, there are some additional | |
207 | * configuration items that the driver uses to drive the port pins. | |
208 | */ | |
209 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
ea818dbb | 210 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
212 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
80885a9d WD |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * Low Level Configuration Settings | |
216 | * (address mappings, register initial values, etc.) | |
217 | * You should know what you are doing if you make changes here. | |
218 | */ | |
80885a9d WD |
219 | |
220 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
221 | #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ | |
222 | ||
132ba5fd | 223 | /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ |
80885a9d WD |
224 | |
225 | #if defined (CONFIG_MPC8245) | |
226 | /* Bit-field values for PMCR2. */ | |
227 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ |
229 | #define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ | |
80885a9d WD |
230 | #endif |
231 | ||
232 | /* Bit-field values for MIOCR1. */ | |
233 | #if !defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 234 | #define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ |
80885a9d WD |
235 | #endif |
236 | /* Bit-field values for MIOCR2. */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ |
80885a9d WD |
238 | /* - note bottom 3 bits MUST be 0 */ |
239 | #endif | |
240 | ||
241 | /* Bit-field values for MCCR1. */ | |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
243 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
80885a9d WD |
244 | |
245 | /* Bit-field values for MCCR2. */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ |
80885a9d | 247 | #if defined (CONFIG_133MHZ_DRAM) |
6d0f6bcf | 248 | #define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */ |
80885a9d | 249 | #else /* refresh cycles */ |
6d0f6bcf | 250 | #define CONFIG_SYS_REFINT 750 |
80885a9d WD |
251 | #endif |
252 | ||
253 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ | |
254 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 255 | #define CONFIG_SYS_BSTOPRE 1023 |
80885a9d | 256 | #else |
6d0f6bcf | 257 | #define CONFIG_SYS_BSTOPRE 250 |
80885a9d WD |
258 | #endif |
259 | ||
260 | /* Bit-field values for MCCR3. */ | |
261 | /* the following are for SDRAM only */ | |
262 | ||
263 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 264 | #define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */ |
80885a9d | 265 | #else |
6d0f6bcf | 266 | #define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */ |
80885a9d WD |
267 | #endif |
268 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf | 269 | #define CONFIG_SYS_RDLAT 2 /* data latency from read command */ |
80885a9d WD |
270 | #endif |
271 | ||
272 | /* Bit-field values for MCCR4. */ | |
273 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ |
275 | #define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */ | |
276 | #define CONFIG_SYS_ACTORW 5 /* Activate to R/W */ | |
277 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
80885a9d WD |
278 | #else |
279 | #if 0 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
281 | #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ | |
282 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
283 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ | |
80885a9d | 284 | #endif |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
286 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
287 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
288 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
80885a9d | 289 | #endif |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ |
291 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ | |
292 | #define CONFIG_SYS_REGDIMM 0 | |
80885a9d | 293 | #if defined (CONFIG_MPC8240) |
6d0f6bcf | 294 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0 |
80885a9d | 295 | #elif defined (CONFIG_MPC8245) |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
297 | #define CONFIG_SYS_EXTROM 0 | |
80885a9d WD |
298 | #else |
299 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
300 | #endif | |
301 | ||
302 | ||
303 | /*----------------------------------------------------------------------- | |
304 | memory bank settings | |
305 | * only bits 20-29 are actually used from these vales to set the | |
306 | * start/end address the upper two bits will be 0, and the lower 20 | |
307 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
308 | * end address | |
309 | */ | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_BANK0_START 0x00000000 |
311 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
312 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
313 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
314 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
315 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
316 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
317 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
318 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
319 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
320 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
321 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
322 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
323 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
324 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
325 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
326 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
327 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
328 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
329 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
330 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
331 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
332 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
333 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
80885a9d WD |
334 | |
335 | /*----------------------------------------------------------------------- | |
336 | * Memory bank enable bitmask, specifying which of the banks defined above | |
337 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
338 | */ | |
6d0f6bcf | 339 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
80885a9d WD |
340 | |
341 | #if defined (CONFIG_MPC8240) | |
6d0f6bcf | 342 | #define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */ |
80885a9d WD |
343 | /* see 8240 book for bit definitions */ |
344 | #elif defined (CONFIG_MPC8245) | |
345 | #if defined (CONFIG_133MHZ_DRAM) | |
6d0f6bcf | 346 | #define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */ |
80885a9d | 347 | #else |
6d0f6bcf | 348 | #define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */ |
80885a9d WD |
349 | #endif |
350 | #else | |
351 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
352 | #endif | |
353 | ||
6d0f6bcf | 354 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
80885a9d WD |
355 | /* currently accessed page in memory */ |
356 | /* see 8240 book for details */ | |
357 | ||
358 | /*----------------------------------------------------------------------- | |
359 | * Block Address Translation (BAT) register settings. | |
360 | */ | |
361 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
363 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d WD |
364 | |
365 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
367 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
80885a9d WD |
368 | |
369 | /* PCI memory */ | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
371 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d WD |
372 | |
373 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
374 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
375 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
80885a9d | 376 | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
378 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
379 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
380 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
381 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
382 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
383 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
384 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
80885a9d WD |
385 | |
386 | ||
387 | /*----------------------------------------------------------------------- | |
388 | * Cache Configuration | |
389 | */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
1bec3d30 | 391 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 392 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
80885a9d WD |
393 | #endif |
394 | ||
80885a9d WD |
395 | /* values according to the manual */ |
396 | #define CONFIG_DRAM_50MHZ 1 | |
397 | #define CONFIG_SDRAM_50MHZ | |
398 | ||
399 | #undef NR_8259_INTS | |
400 | #define NR_8259_INTS 1 | |
401 | ||
402 | /*----------------------------------------------------------------------- | |
403 | * IDE/ATA stuff | |
404 | */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ |
406 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ | |
80885a9d | 407 | |
6d0f6bcf JCPV |
408 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */ |
409 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
410 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
411 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
412 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
413 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
80885a9d WD |
414 | |
415 | #define CONFIG_ATAPI | |
416 | ||
417 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
418 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
419 | #undef CONFIG_IDE_RESET /* reset for ide supported... */ | |
420 | #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
421 | ||
422 | /*----------------------------------------------------------------------- | |
423 | * DISK Partition support | |
424 | */ | |
425 | #define CONFIG_DOS_PARTITION | |
426 | ||
427 | /*----------------------------------------------------------------------- | |
428 | * For booting Linux, the board info and command line data | |
429 | * have to be in the first 8 MB of memory, since this is | |
430 | * the maximum mapped by the Linux kernel during initialization. | |
431 | */ | |
6d0f6bcf | 432 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
80885a9d WD |
433 | |
434 | #endif /* __CONFIG_H */ |