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Commit | Line | Data |
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9acb626f | 1 | /* |
eb0b43f2 | 2 | * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) |
9acb626f | 3 | * |
35cf3b57 | 4 | * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> |
9acb626f | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
9acb626f HS |
7 | */ |
8 | ||
eb0b43f2 JS |
9 | #ifndef _CONFIG_EB_CPU5282_H_ |
10 | #define _CONFIG_EB_CPU5282_H_ | |
9acb626f | 11 | |
6d0f6bcf | 12 | #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP |
b1d71358 | 13 | |
35cf3b57 JS |
14 | /*----------------------------------------------------------------------* |
15 | * High Level Configuration Options (easy to change) * | |
16 | *----------------------------------------------------------------------*/ | |
9acb626f HS |
17 | |
18 | #define CONFIG_MCF52x2 /* define processor family */ | |
19 | #define CONFIG_M5282 /* define processor type */ | |
20 | ||
21 | #define CONFIG_MISC_INIT_R | |
22 | ||
870470db | 23 | #define CONFIG_MCFUART |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
d858c335 | 25 | #define CONFIG_BAUDRATE 115200 |
9acb626f | 26 | |
35cf3b57 | 27 | #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ |
9acb626f HS |
28 | |
29 | #define CONFIG_BOOTCOMMAND "printenv" | |
30 | ||
35cf3b57 JS |
31 | /*----------------------------------------------------------------------* |
32 | * Options * | |
33 | *----------------------------------------------------------------------*/ | |
34 | ||
35 | #define CONFIG_BOOT_RETRY_TIME -1 | |
36 | #define CONFIG_RESET_TO_RETRY | |
37 | #define CONFIG_SPLASH_SCREEN | |
38 | ||
d858c335 JSBE |
39 | #define CONFIG_HW_WATCHDOG |
40 | ||
41 | #define CONFIG_STATUS_LED | |
42 | #define CONFIG_BOARD_SPECIFIC_LED | |
43 | #define STATUS_LED_ACTIVE 0 | |
44 | #define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */ | |
45 | #define STATUS_LED_BOOT 0 | |
46 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
47 | #define STATUS_LED_STATE STATUS_LED_OFF | |
48 | ||
35cf3b57 JS |
49 | /*----------------------------------------------------------------------* |
50 | * Configuration for environment * | |
51 | * Environment is in the second sector of the first 256k of flash * | |
52 | *----------------------------------------------------------------------*/ | |
53 | ||
d858c335 JSBE |
54 | #define CONFIG_ENV_ADDR 0xFF040000 |
55 | #define CONFIG_ENV_SECT_SIZE 0x00020000 | |
5a1aceb0 | 56 | #define CONFIG_ENV_IS_IN_FLASH 1 |
9acb626f | 57 | |
11799434 JL |
58 | /* |
59 | * BOOTP options | |
60 | */ | |
61 | #define CONFIG_BOOTP_BOOTFILESIZE | |
62 | #define CONFIG_BOOTP_BOOTPATH | |
63 | #define CONFIG_BOOTP_GATEWAY | |
64 | #define CONFIG_BOOTP_HOSTNAME | |
65 | ||
dcaa7156 JL |
66 | /* |
67 | * Command line configuration. | |
68 | */ | |
d858c335 | 69 | #define CONFIG_CMDLINE_EDITING |
dcaa7156 JL |
70 | #include <config_cmd_default.h> |
71 | ||
72 | #undef CONFIG_CMD_LOADB | |
d858c335 JSBE |
73 | #define CONFIG_CMD_DATE |
74 | #define CONFIG_CMD_DHCP | |
75 | #define CONFIG_CMD_I2C | |
76 | #define CONFIG_CMD_LED | |
870470db TL |
77 | #define CONFIG_CMD_MII |
78 | #define CONFIG_CMD_NET | |
79 | ||
0e0c4357 TL |
80 | #define CONFIG_MCFTMR |
81 | ||
9acb626f | 82 | #define CONFIG_BOOTDELAY 5 |
eb0b43f2 | 83 | #define CONFIG_SYS_PROMPT "\nEB+CPU5282> " |
35cf3b57 | 84 | #define CONFIG_SYS_LONGHELP 1 |
9acb626f | 85 | |
35cf3b57 | 86 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
35cf3b57 JS |
87 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
88 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
89 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
9acb626f | 90 | |
6d0f6bcf | 91 | #define CONFIG_SYS_LOAD_ADDR 0x20000 |
9acb626f | 92 | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_MEMTEST_START 0x100000 |
94 | #define CONFIG_SYS_MEMTEST_END 0x400000 | |
95 | /*#define CONFIG_SYS_DRAM_TEST 1 */ | |
96 | #undef CONFIG_SYS_DRAM_TEST | |
9acb626f | 97 | |
35cf3b57 JS |
98 | /*----------------------------------------------------------------------* |
99 | * Clock and PLL Configuration * | |
100 | *----------------------------------------------------------------------*/ | |
d858c335 | 101 | #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ |
9acb626f | 102 | |
d858c335 | 103 | /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ |
9acb626f | 104 | |
d858c335 | 105 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
35cf3b57 | 106 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ |
9acb626f | 107 | |
35cf3b57 JS |
108 | /*----------------------------------------------------------------------* |
109 | * Network * | |
110 | *----------------------------------------------------------------------*/ | |
111 | ||
112 | #define CONFIG_MCFFEC | |
35cf3b57 JS |
113 | #define CONFIG_MII 1 |
114 | #define CONFIG_MII_INIT 1 | |
115 | #define CONFIG_SYS_DISCOVER_PHY | |
116 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
117 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
118 | ||
119 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
120 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
121 | #define MCFFEC_TOUT_LOOP 50000 | |
122 | ||
35cf3b57 JS |
123 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
124 | ||
125 | /*------------------------------------------------------------------------- | |
9acb626f HS |
126 | * Low Level Configuration Settings |
127 | * (address mappings, register initial values, etc.) | |
128 | * You should know what you are doing if you make changes here. | |
35cf3b57 JS |
129 | *-----------------------------------------------------------------------*/ |
130 | ||
131 | #define CONFIG_SYS_MBAR 0x40000000 | |
9acb626f | 132 | |
9acb626f HS |
133 | /*----------------------------------------------------------------------- |
134 | * Definitions for initial stack pointer and data area (in DPRAM) | |
35cf3b57 JS |
135 | *-----------------------------------------------------------------------*/ |
136 | ||
137 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 | |
d858c335 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
35cf3b57 | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 140 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 141 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9acb626f HS |
142 | |
143 | /*----------------------------------------------------------------------- | |
144 | * Start addresses for the final memory configuration | |
145 | * (Set up by the startup code) | |
6d0f6bcf | 146 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
9acb626f | 147 | */ |
d858c335 JSBE |
148 | #define CONFIG_SYS_SDRAM_BASE0 0x00000000 |
149 | #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ | |
9acb626f | 150 | |
d858c335 JSBE |
151 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 |
152 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 | |
9acb626f | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
8c89443e | 155 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
6d0f6bcf | 156 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
9acb626f HS |
157 | |
158 | /* | |
159 | * For booting Linux, the board info and command line data | |
160 | * have to be in the first 8 MB of memory, since this is | |
161 | * the maximum mapped by the Linux kernel during initialization ?? | |
162 | */ | |
35cf3b57 | 163 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9acb626f HS |
164 | |
165 | /*----------------------------------------------------------------------- | |
166 | * FLASH organization | |
167 | */ | |
d858c335 | 168 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
35cf3b57 JS |
169 | |
170 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
171 | #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 | |
172 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 | |
173 | ||
d858c335 JSBE |
174 | #define CONFIG_SYS_MAX_FLASH_SECT 128 |
175 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 |
177 | #define CONFIG_SYS_FLASH_PROTECTION | |
9acb626f | 178 | |
d858c335 JSBE |
179 | #define CONFIG_SYS_FLASH_CFI |
180 | #define CONFIG_FLASH_CFI_DRIVER | |
181 | #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 | |
182 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
183 | ||
184 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
185 | ||
9acb626f HS |
186 | /*----------------------------------------------------------------------- |
187 | * Cache Configuration | |
188 | */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
9acb626f | 190 | |
dd9f054e | 191 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 192 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 193 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 194 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
195 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
196 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
197 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
198 | CF_ACR_EN | CF_ACR_SM_ALL) | |
199 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
200 | CF_CACR_CEIB | CF_CACR_DBWE | \ | |
201 | CF_CACR_EUSP) | |
202 | ||
9acb626f HS |
203 | /*----------------------------------------------------------------------- |
204 | * Memory bank definitions | |
205 | */ | |
206 | ||
d858c335 | 207 | #define CONFIG_SYS_CS0_BASE 0xFF000000 |
012522fe | 208 | #define CONFIG_SYS_CS0_CTRL 0x00001980 |
d858c335 | 209 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 |
9acb626f | 210 | |
d858c335 JSBE |
211 | #define CONFIG_SYS_CS2_BASE 0xE0000000 |
212 | #define CONFIG_SYS_CS2_CTRL 0x00001980 | |
213 | #define CONFIG_SYS_CS2_MASK 0x000F0001 | |
214 | ||
215 | #define CONFIG_SYS_CS3_BASE 0xE0100000 | |
216 | #define CONFIG_SYS_CS3_CTRL 0x00001980 | |
012522fe | 217 | #define CONFIG_SYS_CS3_MASK 0x000F0001 |
9acb626f HS |
218 | |
219 | /*----------------------------------------------------------------------- | |
220 | * Port configuration | |
221 | */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
223 | #define CONFIG_SYS_PADDR 0x0000000 | |
224 | #define CONFIG_SYS_PADAT 0x0000000 | |
9acb626f | 225 | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ |
227 | #define CONFIG_SYS_PBDDR 0x0000000 | |
228 | #define CONFIG_SYS_PBDAT 0x0000000 | |
9acb626f | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ |
231 | #define CONFIG_SYS_PCDDR 0x0000000 | |
232 | #define CONFIG_SYS_PCDAT 0x0000000 | |
9acb626f | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ |
235 | #define CONFIG_SYS_PCDDR 0x0000000 | |
236 | #define CONFIG_SYS_PCDAT 0x0000000 | |
9acb626f | 237 | |
d858c335 | 238 | #define CONFIG_SYS_PASPAR 0x0F0F |
6d0f6bcf | 239 | #define CONFIG_SYS_PEHLPAR 0xC0 |
35cf3b57 | 240 | #define CONFIG_SYS_PUAPAR 0x0F |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_DDRUA 0x05 |
242 | #define CONFIG_SYS_PJPAR 0xFF | |
9acb626f | 243 | |
d858c335 JSBE |
244 | /*----------------------------------------------------------------------- |
245 | * I2C | |
246 | */ | |
247 | ||
00f792e0 HS |
248 | #define CONFIG_SYS_I2C |
249 | #define CONFIG_SYS_I2C_FSL | |
d858c335 | 250 | |
00f792e0 | 251 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 |
d858c335 JSBE |
252 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
253 | ||
00f792e0 HS |
254 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 |
255 | #define CONFIG_SYS_FSL_I2C_SLAVE 0 | |
d858c335 JSBE |
256 | |
257 | #ifdef CONFIG_CMD_DATE | |
258 | #define CONFIG_RTC_DS1338 | |
259 | #define CONFIG_I2C_RTC_ADDR 0x68 | |
260 | #endif | |
261 | ||
9acb626f | 262 | /*----------------------------------------------------------------------- |
35cf3b57 | 263 | * VIDEO configuration |
9acb626f HS |
264 | */ |
265 | ||
35cf3b57 | 266 | #define CONFIG_VIDEO |
9acb626f | 267 | |
35cf3b57 | 268 | #ifdef CONFIG_VIDEO |
d858c335 | 269 | #define CONFIG_VIDEO_VCXK 1 |
35cf3b57 JS |
270 | |
271 | #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 | |
272 | #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 | |
d858c335 | 273 | #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE |
35cf3b57 JS |
274 | |
275 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT | |
276 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR | |
277 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 | |
278 | ||
279 | #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT | |
280 | #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR | |
281 | #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 | |
282 | ||
283 | #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT | |
284 | #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR | |
285 | #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 | |
286 | ||
287 | #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE | |
288 | #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE | |
289 | #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 | |
290 | ||
291 | #endif /* CONFIG_VIDEO */ | |
9acb626f HS |
292 | #endif /* _CONFIG_M5282EVB_H */ |
293 | /*---------------------------------------------------------------------*/ |