[people/ms/u-boot.git] / include / configs / eb_cpux9k2.h

/*
 * (C) Copyright 2008-2009
 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
 * Jens Scharsig <esw@bus-elektronik.de>
 *
 * Configuation settings for the EB+CPUx9K2 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _CONFIG_EB_CPUx9K2_H_
#define _CONFIG_EB_CPUx9K2_H_

/*--------------------------------------------------------------------------*/

#define CONFIG_AT91RM9200		/* It's an Atmel AT91RM9200 SoC	*/
#define CONFIG_EB_CPUX9K2		/* on an EP+CPUX9K2 Board	*/
#define USE_920T_MMU

#define CONFIG_VERSION_VARIABLE
#define CONFIG_IDENT_STRING	" on EB+CPUx9K2"

#include <asm/hardware.h>	/* needed for port definitions */

#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F

#define MACH_TYPE_EB_CPUX9K2		1977
#define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2
/*--------------------------------------------------------------------------*/
#define CONFIG_SYS_TEXT_BASE 		0x00000000
#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */

#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */


#define CONFIG_BOOT_RETRY_TIME		30
#define CONFIG_CMDLINE_EDITING

#define CONFIG_SYS_PROMPT	"U-Boot> "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

/*
 * ARM asynchronous clock
 */

#define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ		1000
#define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)

#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */

#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL		0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL		0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define CONFIG_SYS_PLLAR_VAL		0x20483E05 /* 179.4048 MHz for PCK */
#define CONFIG_SYS_PLLBR_VAL		0x104C3E0A /* 47.3088 MHz (for USB) */
#define CONFIG_SYS_MCKR_VAL		0x00000202 /* PCK/3 = MCK Clock */

/*
 * Size of malloc() pool
 */

#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 520*1024)

/*
 * sdram
 */

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR		0x00204000  /* use internal SRAM */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
					CONFIG_SYS_MALLOC_LEN)

#define CONFIG_SYS_PIOC_ASR_VAL		0xFFFF0000 /* PIOC as D16/D31 */
#define CONFIG_SYS_PIOC_BSR_VAL		0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL		0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL		0x00000002 /* CS1=SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL		0x2188c159 /* set up the SDRAM */
#define CONFIG_SYS_SDRAM		0x20000000 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1		0x20000080 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL		0x00000000 /* value written to SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL		0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1		0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2		0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3		0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL		0x000002E0 /* Write refresh rate */

/*
 * Command line configuration
 */

#include <config_cmd_default.h>

#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_I2C_CMD_NO_FLAT
#define CONFIG_I2C_CMD_TREE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT

#define CONFIG_SYS_LONGHELP

/*
 * Filesystems
 */

#define CONFIG_JFFS2_NAND		1

#ifndef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV 		"nand0"
#define CONFIG_JFFS2_PART_OFFSET 	0
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#else
#define MTDIDS_DEFAULT		"nor0=0,nand0=1"
#define MTDPARTS_DEFAULT	"mtdparts="				\
					"0:"				\
					"384k(U-Boot),"			\
					"128k(Env),"			\
					"128k(Splash)," 		\
					"4M(Kernel),"			\
					"-(FS)"				\
					";"				\
					"1:"				\
					"-(jffs2)"
#endif /* CONFIG_JFFS2_CMDLINE */

/*
 * Hardware drivers
 */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_AT91C_PQFP_UHPBUG
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_EFI_PARTITION

#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00300000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"

/*
 * UART/CONSOLE
 */

#define CONFIG_BAUDRATE 115200
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
#define CONFIG_USART_ID		0/* ignored in arm */

/*
 * network
 */

#define CONFIG_NET_RETRY_COUNT		10
#define CONFIG_RESET_PHY_R		1

#define CONFIG_DRIVER_AT91EMAC		1
#define CONFIG_DRIVER_AT91EMAC_QUIET	1
#define CONFIG_SYS_RX_ETH_BUFFER	8
#define CONFIG_MII			1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * I2C-Bus
 */

#define CONFIG_SYS_I2C_SPEED		50000
#define CONFIG_SYS_I2C_SLAVE		0 		/* not used */

#ifndef CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C

/* Software  I2C driver configuration */

#define AT91_PIN_SDA			(1<<25)		/* AT91C_PIO_PA25 */
#define AT91_PIN_SCL			(1<<26)		/* AT91C_PIO_PA26 */

#define CONFIG_SYS_I2C_INIT_BOARD

#define I2C_INIT	i2c_init_board();
#define I2C_ACTIVE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
#define I2C_TRISTATE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
#define I2C_READ	((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
#define I2C_SDA(bit)						\
	if (bit)						\
		writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);	\
	else							\
		writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
#define I2C_SCL(bit)						\
	if (bit)						\
		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);	\
	else							\
		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);

#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)

#endif	/* CONFIG_HARD_I2C */

/* I2C-RTC */

#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#endif

/* EEPROM */

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50

/* FLASH organization */

/*  NOR-FLASH */
#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_FLASH_CFI_DRIVER	1

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x01000000  /* 16 megs main flash */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_PROTECTION	1
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	512
#define CONFIG_SYS_FLASH_ERASE_TOUT	6000
#define CONFIG_SYS_FLASH_WRITE_TOUT	2000

/* NAND */

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1

/* Status LED's */

#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1

#define STATUS_LED_BOOT			1
#define STATUS_LED_ACTIVE		0

#define STATUS_LED_BIT			1	/* AT91C_PIO_PD0 green LED */
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE 		STATUS_LED_OFF		/* BLINKING */
#define STATUS_LED_BIT1			2	/* AT91C_PIO_PD1  red LED */
#define STATUS_LED_STATE1		STATUS_LED_ON		/* BLINKING */
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 4)

#define	CONFIG_VIDEO			1

/* Options */

#ifdef CONFIG_VIDEO

#define CONFIG_VIDEO_VCXK			1

#define CONFIG_SPLASH_SCREEN			1

#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	4
#define CONFIG_SYS_VCXK_BASE	0x30000000

#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		(1<<3)
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	piob
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		odr

#define CONFIG_SYS_VCXK_ENABLE_PIN		(1<<5)
#define CONFIG_SYS_VCXK_ENABLE_PORT		piob
#define CONFIG_SYS_VCXK_ENABLE_DDR		oer

#define CONFIG_SYS_VCXK_REQUEST_PIN		(1<<2)
#define CONFIG_SYS_VCXK_REQUEST_PORT		piob
#define CONFIG_SYS_VCXK_REQUEST_DDR		oer

#define CONFIG_SYS_VCXK_INVERT_PIN		(1<<4)
#define CONFIG_SYS_VCXK_INVERT_PORT		piob
#define CONFIG_SYS_VCXK_INVERT_DDR		oer

#define CONFIG_SYS_VCXK_RESET_PIN		(1<<6)
#define CONFIG_SYS_VCXK_RESET_PORT		piob
#define CONFIG_SYS_VCXK_RESET_DDR		oer

#endif	/* CONFIG_VIDEO */

/* Environment */

#define CONFIG_BOOTDELAY		5

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_SIZE			0x20000 /* sectors are 128K here */

#define CONFIG_BAUDRATE 		115200

#define CONFIG_BOOTCOMMAND		"run nfsboot"

#define CONFIG_NFSBOOTCOMMAND 						\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"run bootargsdefaults;"					\
		"set bootargs $(bootargs) boot=nfs "			\
		";echo $(bootargs)"					\
	";bootm"

#define CONFIG_EXTRA_ENV_SETTINGS 					\
	"displaywidth=256\0"						\
	"displayheight=512\0"						\
	"displaybsteps=1023\0"						\
	"ubootaddr=10000000\0"						\
	"splashimage=10080000\0"					\
	"kerneladdr=100A0000\0"						\
	"kernelsize=00400000\0"						\
	"rootfsaddr=104A0000\0"						\
	"copy_addr=21200000\0"						\
	"rootfssize=00B60000\0"						\
	"bootargsdefaults=set bootargs "				\
		"console=ttyS0,115200 "					\
		"video=vcxk_fb:xres:${displaywidth},"			\
			"yres:${displayheight},"			\
			"bres:${displaybsteps} "			\
		"mem=62M "						\
		"panic=10 "						\
		"uboot=\\\"${ver}\\\" "					\
		"\0"							\
	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"erase $(kerneladdr) +$(kernelsize);"			\
		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
		"protect on $(kerneladdr) +$(kernelsize)"		\
		"\0"							\
	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
		"dhcp $(copy_addr) rfs;"				\
		"erase $(rootfsaddr) +$(rootfssize);"			\
		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
		"\0"							\
	"update_uboot=protect off 10000000 1005FFFF;"			\
		"dhcp $(copy_addr) u-boot_eb_cpux9k2;"			\
		"erase 10000000 1005FFFF;"				\
		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
		"protect on 10000000 1005FFFF;reset\0"			\
	"update_splash=protect off $(splashimage) +20000;"		\
		"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"		\
		"erase $(splashimage) +20000;"				\
		"cp.b $(fileaddr) 10080000 $(filesize);"		\
		"protect on $(splashimage) +20000;reset\0"		\
	"emergency=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(kerneladdr)\0"				\
	"netemergency=run bootargsdefaults;"				\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(copy_addr)\0"					\
	"norboot=run bootargsdefaults;"					\
		"set bootargs $(bootargs) root=initramfs boot=local "	\
		";bootm $(kerneladdr)\0"				\
	"nandboot=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=nand "	\
		";bootm $(kerneladdr)\0"				\
	" "

/*--------------------------------------------------------------------------*/

#endif

/* EOF */
Commit	Line	Data
77e7273c JS	1	/*
	2	* (C) Copyright 2008-2009
	3	* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
	4	* Jens Scharsig <esw@bus-elektronik.de>
	5	*
	6	* Configuation settings for the EB+CPUx9K2 board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef _CONFIG_EB_CPUx9K2_H_
	28	#define _CONFIG_EB_CPUx9K2_H_
	29
	30	/--------------------------------------------------------------------------/
	31
80733994 JS	32	#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
	33	#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
	34	#define USE_920T_MMU
77e7273c	35
80733994	36	#define CONFIG_VERSION_VARIABLE
77e7273c JS	37	#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
77e7273c JS	38
6a372e94	39	#include <asm/hardware.h> /* needed for port definitions */
77e7273c JS	40
77e7273c JS	41	#define CONFIG_MISC_INIT_R
5a05cb73	42	#define CONFIG_BOARD_EARLY_INIT_F
77e7273c	43
2026a119 JS	44	#define MACH_TYPE_EB_CPUX9K2 1977
2026a119 JS	45	#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
77e7273c	46	/--------------------------------------------------------------------------/
cebcf7da	47	#define CONFIG_SYS_TEXT_BASE 0x00000000
77e7273c JS	48	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
	49
	50	#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
	51	#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
	52	#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
	53
	54
	55	#define CONFIG_BOOT_RETRY_TIME 30
	56	#define CONFIG_CMDLINE_EDITING
	57
	58	#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
	59	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	60	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	61	#define CONFIG_SYS_PBSIZE \
	62	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	63
	64	#define CONFIG_STACKSIZE (321024) / regular stack */
	65
	66	/*
	67	* ARM asynchronous clock
	68	*/
	69
	70	#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
	71	#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
	72	#define CONFIG_SYS_HZ 1000
	73	#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
	74
6a372e94	75	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
77e7273c JS	76
	77	#define CONFIG_CMDLINE_TAG 1
	78	#define CONFIG_SETUP_MEMORY_TAGS 1
	79	#define CONFIG_INITRD_TAG 1
	80
	81	#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
	82	/* flash */
	83	#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
	84	#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	85
	86	/* clocks */
	87	#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
	88	#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
	89	#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
	90
	91	/*
	92	* Size of malloc() pool
	93	*/
	94
	95	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
77e7273c JS	96
	97	/*
	98	* sdram
	99	*/
	100
	101	#define CONFIG_NR_DRAM_BANKS 1
77e7273c	102
cebcf7da JS	103	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	104	#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	105	#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
	106
	107	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
77e7273c	108	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
cebcf7da	109	CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
77e7273c JS	110	CONFIG_SYS_MALLOC_LEN)
	111
	112	#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
	113	#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
	114	#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
	115	#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	116	#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
	117	#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
	118	#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
	119	#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
	120	#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
	121	#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
	122	#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	123	#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	124	#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
	125
	126	/*
	127	* Command line configuration
	128	*/
	129
	130	#include <config_cmd_default.h>
	131
	132	#define CONFIG_CMD_BMP
	133	#define CONFIG_CMD_DATE
	134	#define CONFIG_CMD_DHCP
	135	#define CONFIG_CMD_I2C
	136	#define CONFIG_CMD_JFFS2
	137	#define CONFIG_CMD_MII
	138	#define CONFIG_CMD_NAND
	139	#define CONFIG_CMD_PING
	140	#define CONFIG_I2C_CMD_NO_FLAT
	141	#define CONFIG_I2C_CMD_TREE
0d62032e JS	142	#define CONFIG_CMD_USB
0d62032e JS	143	#define CONFIG_CMD_FAT
77e7273c JS	144
	145	#define CONFIG_SYS_LONGHELP
	146
	147	/*
	148	* Filesystems
	149	*/
	150
	151	#define CONFIG_JFFS2_NAND 1
	152
	153	#ifndef CONFIG_JFFS2_CMDLINE
	154	#define CONFIG_JFFS2_DEV "nand0"
	155	#define CONFIG_JFFS2_PART_OFFSET 0
	156	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	157	#else
	158	#define MTDIDS_DEFAULT "nor0=0,nand0=1"
	159	#define MTDPARTS_DEFAULT "mtdparts=" \
	160	"0:" \
	161	"384k(U-Boot)," \
	162	"128k(Env)," \
	163	"128k(Splash)," \
	164	"4M(Kernel)," \
	165	"-(FS)" \
	166	";" \
	167	"1:" \
	168	"-(jffs2)"
	169	#endif /* CONFIG_JFFS2_CMDLINE */
	170
	171	/*
	172	* Hardware drivers
	173	*/
0d62032e JS	174	#define CONFIG_USB_ATMEL
	175	#define CONFIG_USB_OHCI_NEW
	176	#define CONFIG_AT91C_PQFP_UHPBUG
	177	#define CONFIG_USB_STORAGE
	178	#define CONFIG_DOS_PARTITION
	179	#define CONFIG_ISO_PARTITION
	180	#define CONFIG_EFI_PARTITION
	181
	182	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
	183	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	184	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
	185	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
77e7273c JS	186
	187	/*
	188	* UART/CONSOLE
	189	*/
	190
77e7273c	191	#define CONFIG_BAUDRATE 115200
5a05cb73 AB	192	#define CONFIG_ATMEL_USART
	193	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	194	#define CONFIG_USART_ID 0/* ignored in arm */
77e7273c JS	195
	196	/*
	197	* network
	198	*/
77e7273c JS	199
	200	#define CONFIG_NET_RETRY_COUNT 10
	201	#define CONFIG_RESET_PHY_R 1
	202
	203	#define CONFIG_DRIVER_AT91EMAC 1
	204	#define CONFIG_DRIVER_AT91EMAC_QUIET 1
	205	#define CONFIG_SYS_RX_ETH_BUFFER 8
	206	#define CONFIG_MII 1
	207
	208	/*
	209	* BOOTP options
	210	*/
	211	#define CONFIG_BOOTP_BOOTFILESIZE
	212	#define CONFIG_BOOTP_BOOTPATH
	213	#define CONFIG_BOOTP_GATEWAY
	214	#define CONFIG_BOOTP_HOSTNAME
	215
	216	/*
	217	* I2C-Bus
	218	*/
	219
	220	#define CONFIG_SYS_I2C_SPEED 50000
	221	#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
	222
	223	#ifndef CONFIG_HARD_I2C
	224	#define CONFIG_SOFT_I2C
	225
	226	/* Software I2C driver configuration */
	227
	228	#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
	229	#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
	230
	231	#define CONFIG_SYS_I2C_INIT_BOARD
	232
	233	#define I2C_INIT i2c_init_board();
80733994 JS	234	#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
	235	#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
	236	#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
77e7273c JS	237	#define I2C_SDA(bit) \
77e7273c JS	238	if (bit) \
80733994	239	writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
77e7273c	240	else \
80733994	241	writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
77e7273c JS	242	#define I2C_SCL(bit) \
77e7273c JS	243	if (bit) \
80733994	244	writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
77e7273c	245	else \
80733994	246	writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
77e7273c JS	247
	248	#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
	249
	250	#endif /* CONFIG_HARD_I2C */
	251
	252	/* I2C-RTC */
	253
	254	#ifdef CONFIG_CMD_DATE
	255	#define CONFIG_RTC_DS1338
	256	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	257	#endif
	258
	259	/* EEPROM */
	260
	261	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	262	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	263
	264	/* FLASH organization */
	265
	266	/* NOR-FLASH */
cebcf7da	267	#define CONFIG_FLASH_SHOW_PROGRESS 45
77e7273c JS	268
	269	#define CONFIG_FLASH_CFI_DRIVER 1
	270
	271	#define PHYS_FLASH_1 0x10000000
	272	#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
	273	#define CONFIG_SYS_FLASH_CFI 1
	274	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	275
	276	#define CONFIG_SYS_FLASH_PROTECTION 1
	277	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	278	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	279	#define CONFIG_SYS_MAX_FLASH_SECT 512
	280	#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
	281	#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
	282
	283	/* NAND */
	284
77e7273c JS	285	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	286	#define CONFIG_SYS_NAND_BASE 0x40000000
	287	#define CONFIG_SYS_NAND_DBW_8 1
	288
77e7273c JS	289	/* Status LED's */
	290
	291	#define CONFIG_STATUS_LED 1
	292	#define CONFIG_BOARD_SPECIFIC_LED 1
	293
	294	#define STATUS_LED_BOOT 1
	295	#define STATUS_LED_ACTIVE 0
	296
	297	#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
	298	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	299	#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
	300	#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
	301	#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
	302	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
	303
	304	#define CONFIG_VIDEO 1
	305
	306	/* Options */
	307
	308	#ifdef CONFIG_VIDEO
	309
	310	#define CONFIG_VIDEO_VCXK 1
	311
	312	#define CONFIG_SPLASH_SCREEN 1
	313
	314	#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
	315	#define CONFIG_SYS_VCXK_BASE 0x30000000
	316
	317	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
	318	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
	319	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
	320
	321	#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
	322	#define CONFIG_SYS_VCXK_ENABLE_PORT piob
	323	#define CONFIG_SYS_VCXK_ENABLE_DDR oer
	324
	325	#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
	326	#define CONFIG_SYS_VCXK_REQUEST_PORT piob
	327	#define CONFIG_SYS_VCXK_REQUEST_DDR oer
	328
	329	#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
	330	#define CONFIG_SYS_VCXK_INVERT_PORT piob
	331	#define CONFIG_SYS_VCXK_INVERT_DDR oer
	332
	333	#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
	334	#define CONFIG_SYS_VCXK_RESET_PORT piob
	335	#define CONFIG_SYS_VCXK_RESET_DDR oer
	336
	337	#endif /* CONFIG_VIDEO */
	338
	339	/* Environment */
	340
	341	#define CONFIG_BOOTDELAY 5
	342
	343	#define CONFIG_ENV_IS_IN_FLASH 1
	344	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
	345	#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
	346
	347	#define CONFIG_BAUDRATE 115200
	348
	349	#define CONFIG_BOOTCOMMAND "run nfsboot"
	350
	351	#define CONFIG_NFSBOOTCOMMAND \
	352	"dhcp $(copy_addr) uImage_cpux9k2;" \
353	"run bootargsdefaults;" \
354	"set bootargs $(bootargs) boot=nfs " \
355	";echo $(bootargs)" \
356	";bootm"
357
358	#define CONFIG_EXTRA_ENV_SETTINGS \
359	"displaywidth=256\0" \
360	"displayheight=512\0" \
361	"displaybsteps=1023\0" \
362	"ubootaddr=10000000\0" \
363	"splashimage=10080000\0" \
364	"kerneladdr=100A0000\0" \
365	"kernelsize=00400000\0" \
366	"rootfsaddr=104A0000\0" \
367	"copy_addr=21200000\0" \
368	"rootfssize=00B60000\0" \
369	"bootargsdefaults=set bootargs " \
370	"console=ttyS0,115200 " \
371	"video=vcxk_fb:xres:${displaywidth}," \
372	"yres:${displayheight}," \
373	"bres:${displaybsteps} " \
374	"mem=62M " \
375	"panic=10 " \
376	"uboot=\\\"${ver}\\\" " \
377	"\0" \
378	"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
379	"dhcp $(copy_addr) uImage_cpux9k2;" \
380	"erase $(kerneladdr) +$(kernelsize);" \
381	"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
382	"protect on $(kerneladdr) +$(kernelsize)" \
383	"\0" \
384	"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
385	"dhcp $(copy_addr) rfs;" \
386	"erase $(rootfsaddr) +$(rootfssize);" \
387	"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
388	"\0" \
389	"update_uboot=protect off 10000000 1005FFFF;" \
390	"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
391	"erase 10000000 1005FFFF;" \
392	"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
393	"protect on 10000000 1005FFFF;reset\0" \
394	"update_splash=protect off $(splashimage) +20000;" \
395	"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
396	"erase $(splashimage) +20000;" \
397	"cp.b $(fileaddr) 10080000 $(filesize);" \
398	"protect on $(splashimage) +20000;reset\0" \
399	"emergency=run bootargsdefaults;" \
400	"set bootargs $(bootargs) root=initramfs boot=emergency " \
401	";bootm $(kerneladdr)\0" \
402	"netemergency=run bootargsdefaults;" \
403	"dhcp $(copy_addr) uImage_cpux9k2;" \
404	"set bootargs $(bootargs) root=initramfs boot=emergency " \
405	";bootm $(copy_addr)\0" \
406	"norboot=run bootargsdefaults;" \
407	"set bootargs $(bootargs) root=initramfs boot=local " \
408	";bootm $(kerneladdr)\0" \
409	"nandboot=run bootargsdefaults;" \
410	"set bootargs $(bootargs) root=initramfs boot=nand " \
411	";bootm $(kerneladdr)\0" \
77e7273c JS	412	" "
	413
	414	/--------------------------------------------------------------------------/
	415
	416	#endif
	417
	418	/* EOF */