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77e7273c JS |
1 | /* |
2 | * (C) Copyright 2008-2009 | |
3 | * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de> | |
4 | * Jens Scharsig <esw@bus-elektronik.de> | |
5 | * | |
6 | * Configuation settings for the EB+CPUx9K2 board. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
77e7273c JS |
9 | */ |
10 | ||
11 | #ifndef _CONFIG_EB_CPUx9K2_H_ | |
12 | #define _CONFIG_EB_CPUx9K2_H_ | |
13 | ||
14 | /*--------------------------------------------------------------------------*/ | |
15 | ||
80733994 JS |
16 | #define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */ |
17 | #define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */ | |
18 | #define USE_920T_MMU | |
77e7273c | 19 | |
80733994 | 20 | #define CONFIG_VERSION_VARIABLE |
77e7273c JS |
21 | #define CONFIG_IDENT_STRING " on EB+CPUx9K2" |
22 | ||
6a372e94 | 23 | #include <asm/hardware.h> /* needed for port definitions */ |
77e7273c JS |
24 | |
25 | #define CONFIG_MISC_INIT_R | |
5a05cb73 | 26 | #define CONFIG_BOARD_EARLY_INIT_F |
77e7273c | 27 | |
2026a119 JS |
28 | #define MACH_TYPE_EB_CPUX9K2 1977 |
29 | #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 | |
cc69cc00 JSBE |
30 | |
31 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
32 | #define CONFIG_SYS_DCACHE_OFF | |
33 | ||
77e7273c | 34 | /*--------------------------------------------------------------------------*/ |
503e159b JS |
35 | #ifndef CONFIG_RAMBOOT |
36 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
37 | #else | |
38 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
f89a6ee3 | 39 | #define CONFIG_SYS_TEXT_BASE 0x21800000 |
503e159b | 40 | #endif |
77e7273c | 41 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
bc695898 | 42 | #define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 |
77e7273c | 43 | |
77e7273c JS |
44 | #define CONFIG_BOOT_RETRY_TIME 30 |
45 | #define CONFIG_CMDLINE_EDITING | |
46 | ||
47 | #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ | |
48 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
49 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
50 | #define CONFIG_SYS_PBSIZE \ | |
51 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
52 | ||
77e7273c JS |
53 | /* |
54 | * ARM asynchronous clock | |
55 | */ | |
56 | ||
57 | #define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */ | |
58 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) | |
77e7273c JS |
59 | #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) |
60 | ||
6a372e94 | 61 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ |
77e7273c JS |
62 | |
63 | #define CONFIG_CMDLINE_TAG 1 | |
64 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
65 | #define CONFIG_INITRD_TAG 1 | |
66 | ||
67 | #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 | |
68 | /* flash */ | |
69 | #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 | |
70 | #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ | |
71 | ||
72 | /* clocks */ | |
73 | #define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */ | |
74 | #define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */ | |
75 | #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */ | |
76 | ||
77 | /* | |
78 | * Size of malloc() pool | |
79 | */ | |
80 | ||
db824479 | 81 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
77e7273c JS |
82 | |
83 | /* | |
84 | * sdram | |
85 | */ | |
86 | ||
87 | #define CONFIG_NR_DRAM_BANKS 1 | |
77e7273c | 88 | |
cebcf7da JS |
89 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
90 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
91 | #define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ | |
92 | ||
93 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
77e7273c | 94 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ |
cebcf7da | 95 | CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ |
77e7273c JS |
96 | CONFIG_SYS_MALLOC_LEN) |
97 | ||
98 | #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ | |
99 | #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 | |
100 | #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 | |
101 | #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ | |
102 | #define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */ | |
103 | #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ | |
104 | #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ | |
105 | #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ | |
106 | #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ | |
107 | #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ | |
108 | #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ | |
109 | #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ | |
110 | #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ | |
111 | ||
112 | /* | |
113 | * Command line configuration | |
114 | */ | |
115 | ||
116 | #include <config_cmd_default.h> | |
117 | ||
118 | #define CONFIG_CMD_BMP | |
119 | #define CONFIG_CMD_DATE | |
120 | #define CONFIG_CMD_DHCP | |
121 | #define CONFIG_CMD_I2C | |
77e7273c JS |
122 | #define CONFIG_CMD_MII |
123 | #define CONFIG_CMD_NAND | |
124 | #define CONFIG_CMD_PING | |
77e7273c | 125 | #define CONFIG_I2C_CMD_TREE |
0d62032e JS |
126 | #define CONFIG_CMD_USB |
127 | #define CONFIG_CMD_FAT | |
bc695898 JSBE |
128 | #define CONFIG_CMD_UBI |
129 | #define CONFIG_CMD_MTDPARTS | |
130 | #define CONFIG_CMD_UBIFS | |
f89a6ee3 | 131 | |
77e7273c JS |
132 | #define CONFIG_SYS_LONGHELP |
133 | ||
134 | /* | |
bc695898 | 135 | * MTD defines |
77e7273c JS |
136 | */ |
137 | ||
bc695898 JSBE |
138 | #define CONFIG_FLASH_CFI_MTD |
139 | #define CONFIG_MTD_DEVICE | |
140 | #define CONFIG_MTD_PARTITIONS | |
141 | #define CONFIG_RBTREE | |
142 | #define CONFIG_LZO | |
77e7273c | 143 | |
bc695898 | 144 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" |
77e7273c | 145 | #define MTDPARTS_DEFAULT "mtdparts=" \ |
bc695898 JSBE |
146 | "physmap-flash.0:" \ |
147 | "512k(U-Boot)," \ | |
148 | "128k(Env)," \ | |
149 | "128k(Splash)," \ | |
150 | "4M(Kernel)," \ | |
151 | "384k(MiniFS)," \ | |
152 | "-(FS)" \ | |
77e7273c | 153 | ";" \ |
bc695898 JSBE |
154 | "atmel_nand:" \ |
155 | "1M(emergency)," \ | |
156 | "-(data)" | |
77e7273c JS |
157 | /* |
158 | * Hardware drivers | |
159 | */ | |
0d62032e | 160 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 161 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
0d62032e JS |
162 | #define CONFIG_USB_OHCI_NEW |
163 | #define CONFIG_AT91C_PQFP_UHPBUG | |
164 | #define CONFIG_USB_STORAGE | |
165 | #define CONFIG_DOS_PARTITION | |
166 | #define CONFIG_ISO_PARTITION | |
167 | #define CONFIG_EFI_PARTITION | |
168 | ||
169 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
170 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
171 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000 | |
172 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" | |
77e7273c JS |
173 | |
174 | /* | |
175 | * UART/CONSOLE | |
176 | */ | |
177 | ||
77e7273c | 178 | #define CONFIG_BAUDRATE 115200 |
5a05cb73 AB |
179 | #define CONFIG_ATMEL_USART |
180 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
181 | #define CONFIG_USART_ID 0/* ignored in arm */ | |
77e7273c JS |
182 | |
183 | /* | |
184 | * network | |
185 | */ | |
77e7273c JS |
186 | |
187 | #define CONFIG_NET_RETRY_COUNT 10 | |
188 | #define CONFIG_RESET_PHY_R 1 | |
189 | ||
190 | #define CONFIG_DRIVER_AT91EMAC 1 | |
191 | #define CONFIG_DRIVER_AT91EMAC_QUIET 1 | |
192 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
193 | #define CONFIG_MII 1 | |
194 | ||
195 | /* | |
196 | * BOOTP options | |
197 | */ | |
198 | #define CONFIG_BOOTP_BOOTFILESIZE | |
199 | #define CONFIG_BOOTP_BOOTPATH | |
200 | #define CONFIG_BOOTP_GATEWAY | |
201 | #define CONFIG_BOOTP_HOSTNAME | |
202 | ||
203 | /* | |
204 | * I2C-Bus | |
205 | */ | |
206 | ||
ea818dbb HS |
207 | #define CONFIG_SYS_I2C |
208 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
209 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
210 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
77e7273c JS |
211 | |
212 | /* Software I2C driver configuration */ | |
213 | ||
214 | #define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */ | |
215 | #define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */ | |
216 | ||
217 | #define CONFIG_SYS_I2C_INIT_BOARD | |
218 | ||
219 | #define I2C_INIT i2c_init_board(); | |
80733994 JS |
220 | #define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr); |
221 | #define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder); | |
222 | #define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0) | |
77e7273c JS |
223 | #define I2C_SDA(bit) \ |
224 | if (bit) \ | |
80733994 | 225 | writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \ |
77e7273c | 226 | else \ |
80733994 | 227 | writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr); |
77e7273c JS |
228 | #define I2C_SCL(bit) \ |
229 | if (bit) \ | |
80733994 | 230 | writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \ |
77e7273c | 231 | else \ |
80733994 | 232 | writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr); |
77e7273c | 233 | |
ea818dbb | 234 | #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED) |
77e7273c JS |
235 | |
236 | /* I2C-RTC */ | |
237 | ||
238 | #ifdef CONFIG_CMD_DATE | |
239 | #define CONFIG_RTC_DS1338 | |
240 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
241 | #endif | |
242 | ||
243 | /* EEPROM */ | |
244 | ||
245 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
246 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
247 | ||
248 | /* FLASH organization */ | |
249 | ||
250 | /* NOR-FLASH */ | |
cebcf7da | 251 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
77e7273c JS |
252 | |
253 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
254 | ||
255 | #define PHYS_FLASH_1 0x10000000 | |
256 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */ | |
257 | #define CONFIG_SYS_FLASH_CFI 1 | |
258 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
259 | ||
260 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
261 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
262 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
263 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
264 | #define CONFIG_SYS_FLASH_ERASE_TOUT 6000 | |
265 | #define CONFIG_SYS_FLASH_WRITE_TOUT 2000 | |
266 | ||
267 | /* NAND */ | |
268 | ||
77e7273c JS |
269 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
270 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
271 | #define CONFIG_SYS_NAND_DBW_8 1 | |
272 | ||
77e7273c JS |
273 | /* Status LED's */ |
274 | ||
275 | #define CONFIG_STATUS_LED 1 | |
276 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
277 | ||
278 | #define STATUS_LED_BOOT 1 | |
279 | #define STATUS_LED_ACTIVE 0 | |
280 | ||
281 | #define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */ | |
282 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
283 | #define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */ | |
284 | #define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */ | |
285 | #define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */ | |
286 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4) | |
287 | ||
288 | #define CONFIG_VIDEO 1 | |
289 | ||
290 | /* Options */ | |
291 | ||
292 | #ifdef CONFIG_VIDEO | |
293 | ||
294 | #define CONFIG_VIDEO_VCXK 1 | |
295 | ||
296 | #define CONFIG_SPLASH_SCREEN 1 | |
297 | ||
298 | #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4 | |
299 | #define CONFIG_SYS_VCXK_BASE 0x30000000 | |
300 | ||
301 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3) | |
302 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob | |
303 | #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr | |
304 | ||
305 | #define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5) | |
306 | #define CONFIG_SYS_VCXK_ENABLE_PORT piob | |
307 | #define CONFIG_SYS_VCXK_ENABLE_DDR oer | |
308 | ||
309 | #define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2) | |
310 | #define CONFIG_SYS_VCXK_REQUEST_PORT piob | |
311 | #define CONFIG_SYS_VCXK_REQUEST_DDR oer | |
312 | ||
313 | #define CONFIG_SYS_VCXK_INVERT_PIN (1<<4) | |
314 | #define CONFIG_SYS_VCXK_INVERT_PORT piob | |
315 | #define CONFIG_SYS_VCXK_INVERT_DDR oer | |
316 | ||
317 | #define CONFIG_SYS_VCXK_RESET_PIN (1<<6) | |
318 | #define CONFIG_SYS_VCXK_RESET_PORT piob | |
319 | #define CONFIG_SYS_VCXK_RESET_DDR oer | |
320 | ||
321 | #endif /* CONFIG_VIDEO */ | |
322 | ||
323 | /* Environment */ | |
324 | ||
325 | #define CONFIG_BOOTDELAY 5 | |
326 | ||
327 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
bc695898 | 328 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000) |
77e7273c JS |
329 | #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ |
330 | ||
331 | #define CONFIG_BAUDRATE 115200 | |
332 | ||
333 | #define CONFIG_BOOTCOMMAND "run nfsboot" | |
334 | ||
335 | #define CONFIG_NFSBOOTCOMMAND \ | |
336 | "dhcp $(copy_addr) uImage_cpux9k2;" \ | |
337 | "run bootargsdefaults;" \ | |
338 | "set bootargs $(bootargs) boot=nfs " \ | |
339 | ";echo $(bootargs)" \ | |
340 | ";bootm" | |
341 | ||
342 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
343 | "displaywidth=256\0" \ | |
344 | "displayheight=512\0" \ | |
345 | "displaybsteps=1023\0" \ | |
346 | "ubootaddr=10000000\0" \ | |
bc695898 JSBE |
347 | "splashimage=100A0000\0" \ |
348 | "kerneladdr=100C0000\0" \ | |
77e7273c | 349 | "kernelsize=00400000\0" \ |
bc695898 | 350 | "rootfsaddr=10520000\0" \ |
77e7273c | 351 | "copy_addr=21200000\0" \ |
bc695898 JSBE |
352 | "rootfssize=00AE0000\0" \ |
353 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
354 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
77e7273c JS |
355 | "bootargsdefaults=set bootargs " \ |
356 | "console=ttyS0,115200 " \ | |
357 | "video=vcxk_fb:xres:${displaywidth}," \ | |
358 | "yres:${displayheight}," \ | |
359 | "bres:${displaybsteps} " \ | |
360 | "mem=62M " \ | |
361 | "panic=10 " \ | |
362 | "uboot=\\\"${ver}\\\" " \ | |
363 | "\0" \ | |
364 | "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ | |
365 | "dhcp $(copy_addr) uImage_cpux9k2;" \ | |
366 | "erase $(kerneladdr) +$(kernelsize);" \ | |
367 | "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ | |
368 | "protect on $(kerneladdr) +$(kernelsize)" \ | |
369 | "\0" \ | |
370 | "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ | |
371 | "dhcp $(copy_addr) rfs;" \ | |
372 | "erase $(rootfsaddr) +$(rootfssize);" \ | |
373 | "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ | |
374 | "\0" \ | |
bc695898 | 375 | "update_uboot=protect off 10000000 1007FFFF;" \ |
77e7273c | 376 | "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ |
bc695898 | 377 | "erase 10000000 1007FFFF;" \ |
77e7273c | 378 | "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ |
bc695898 | 379 | "protect on 10000000 1007FFFF;reset\0" \ |
77e7273c JS |
380 | "update_splash=protect off $(splashimage) +20000;" \ |
381 | "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ | |
382 | "erase $(splashimage) +20000;" \ | |
bc695898 | 383 | "cp.b $(fileaddr) $(splashimage) $(filesize);" \ |
77e7273c JS |
384 | "protect on $(splashimage) +20000;reset\0" \ |
385 | "emergency=run bootargsdefaults;" \ | |
386 | "set bootargs $(bootargs) root=initramfs boot=emergency " \ | |
387 | ";bootm $(kerneladdr)\0" \ | |
388 | "netemergency=run bootargsdefaults;" \ | |
389 | "dhcp $(copy_addr) uImage_cpux9k2;" \ | |
390 | "set bootargs $(bootargs) root=initramfs boot=emergency " \ | |
391 | ";bootm $(copy_addr)\0" \ | |
392 | "norboot=run bootargsdefaults;" \ | |
393 | "set bootargs $(bootargs) root=initramfs boot=local " \ | |
394 | ";bootm $(kerneladdr)\0" \ | |
395 | "nandboot=run bootargsdefaults;" \ | |
396 | "set bootargs $(bootargs) root=initramfs boot=nand " \ | |
397 | ";bootm $(kerneladdr)\0" \ | |
77e7273c JS |
398 | " " |
399 | ||
400 | /*--------------------------------------------------------------------------*/ | |
401 | ||
402 | #endif | |
403 | ||
404 | /* EOF */ |