[people/ms/u-boot.git] / include / configs / ebony.h

/*
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_EBONY		1	    /* Board is ebony		*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/

#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/

#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_NVRAM */

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_FLASH_ADDR0         0x5555
#define CFG_FLASH_ADDR1         0x2aaa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=ebony\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/ebony/uImage\0"				\
	"kernel_addr=ff800000\0"					\
	"ramdisk_addr=ff810000\0"					\
	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		8	/* PHY address			*/

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_ELF	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SDRAM	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			            /* include pci support	        */
#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
acea76a2 WD	1	/*
	2	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/************************************************************************
	24	* board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
	25	***********************************************************************/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*-----------------------------------------------------------------------
	31	* High Level Configuration Options
	32	----------------------------------------------------------------------/
	33	#define CONFIG_EBONY 1 /* Board is ebony */
	34	#define CONFIG_4xx 1 /* ... PPC4xx family */
c837dcb1	35	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
acea76a2 WD	36	#undef CFG_DRAM_TEST /* Disable-takes long time! */
	37	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	38
8a316c9b SR	39	/*
	40	* Define here the location of the environment variables (FLASH or NVRAM).
	41	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	42	* supported for backward compatibility.
	43	*/
	44	#if 1
	45	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	46	#else
	47	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	48	#endif
	49
acea76a2 WD	50	/*-----------------------------------------------------------------------
	51	* Base addresses -- Note these are effective addresses where the
	52	* actual resources get mapped (not physical addresses)
	53	----------------------------------------------------------------------/
	54	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	55	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
8a316c9b	56	#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
acea76a2 WD	57	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	58	#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	59	#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
	60	#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	61
acea76a2	62	#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
8a316c9b	63	#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
acea76a2 WD	64
	65	/*-----------------------------------------------------------------------
	66	* Initial RAM & stack pointer (placed in internal SRAM)
	67	----------------------------------------------------------------------/
	68	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	69	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	70	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	71
	72	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	73	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	74
	75	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	76	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
	77
	78	/*-----------------------------------------------------------------------
	79	* Serial Port
	80	----------------------------------------------------------------------/
	81	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	82	#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
8a316c9b	83	#define CONFIG_BAUDRATE 115200
acea76a2 WD	84
	85	#define CFG_BAUDRATE_TABLE \
	86	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
	87
	88	/*-----------------------------------------------------------------------
	89	* NVRAM/RTC
	90	*
	91	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	92	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	93	* address for the RTC registers is:
	94	*
	95	* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
	96	*
	97	----------------------------------------------------------------------/
	98	#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
	99	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
	100
8a316c9b SR	101	#ifdef CFG_ENV_IS_IN_NVRAM
	102	#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
	103	#define CFG_ENV_ADDR \
	104	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
	105	#endif /* CFG_ENV_IS_IN_NVRAM */
	106
acea76a2 WD	107	/*-----------------------------------------------------------------------
	108	* FLASH related
	109	----------------------------------------------------------------------/
	110	#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
	111	#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
	112
acea76a2 WD	113	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	114	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	115
8a316c9b SR	116	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	117
	118	#define CFG_FLASH_ADDR0 0x5555
	119	#define CFG_FLASH_ADDR1 0x2aaa
	120	#define CFG_FLASH_WORD_SIZE unsigned char
	121
	122	#ifdef CFG_ENV_IS_IN_FLASH
	123	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	124	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	125	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	126
	127	/* Address and size of Redundant Environment Sector */
	128	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	129	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	130	#endif /* CFG_ENV_IS_IN_FLASH */
	131
acea76a2 WD	132	/*-----------------------------------------------------------------------
	133	* DDR SDRAM
	134	----------------------------------------------------------------------/
	135	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
	136	#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
	137
	138	/*-----------------------------------------------------------------------
	139	* I2C
	140	----------------------------------------------------------------------/
	141	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	142	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	143	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	144	#define CFG_I2C_SLAVE 0x7F
	145	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	146
8a316c9b SR	147	#define CONFIG_PREBOOT "echo;" \
	148	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	149	"echo"
	150
	151	#undef CONFIG_BOOTARGS
	152
	153	#define CONFIG_EXTRA_ENV_SETTINGS \
	154	"netdev=eth0\0" \
	155	"hostname=ebony\0" \
	156	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	157	"nfsroot=$(serverip):$(rootpath)\0" \
	158	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	159	"addip=setenv bootargs $(bootargs) " \
	160	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	161	":$(hostname):$(netdev):off panic=1\0" \
	162	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
	163	"flash_nfs=run nfsargs addip addtty;" \
	164	"bootm $(kernel_addr)\0" \
	165	"flash_self=run ramargs addip addtty;" \
	166	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	167	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
	168	"bootm\0" \
	169	"rootpath=/opt/eldk/ppc_4xx\0" \
	170	"bootfile=/tftpboot/ebony/uImage\0" \
	171	"kernel_addr=ff800000\0" \
	172	"ramdisk_addr=ff810000\0" \
	173	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
	174	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	175	"cp.b 100000 fffc0000 40000;" \
	176	"setenv filesize;saveenv\0" \
	177	"upd=run load;run update\0" \
	178	""
	179	#define CONFIG_BOOTCOMMAND "run flash_self"
	180
	181	#if 0
	182	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	183	#else
	184	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	185	#endif
acea76a2	186
8a316c9b	187	#define CONFIG_BAUDRATE 115200
acea76a2 WD	188
	189	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	190	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	191
	192	#define CONFIG_MII 1 /* MII PHY management */
	193	#define CONFIG_PHY_ADDR 8 /* PHY address */
	194
acea76a2	195	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
8a316c9b	196	CFG_CMD_ASKENV \| \
acea76a2	197	CFG_CMD_DATE \| \
8a316c9b SR	198	CFG_CMD_DHCP \| \
	199	CFG_CMD_DIAG \| \
	200	CFG_CMD_ELF \| \
	201	CFG_CMD_I2C \| \
	202	CFG_CMD_IRQ \| \
	203	CFG_CMD_MII \| \
	204	CFG_CMD_NET \| \
	205	CFG_CMD_NFS \| \
	206	CFG_CMD_PCI \| \
	207	CFG_CMD_PING \| \
	208	CFG_CMD_REGINFO \| \
	209	CFG_CMD_SDRAM \| \
	210	CFG_CMD_SNTP )
acea76a2 WD	211
	212	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	213	#include <cmd_confdefs.h>
	214
	215	#undef CONFIG_WATCHDOG /* watchdog disabled */
	216
	217	/*
	218	* Miscellaneous configurable options
	219	*/
	220	#define CFG_LONGHELP /* undef to save memory */
	221	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	222	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	223	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	224	#else
	225	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	226	#endif
	227	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	228	#define CFG_MAXARGS 16 /* max number of command args */
	229	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	230
	231	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	232	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	233
	234	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	235	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	236
	237	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	238
8a316c9b SR	239	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	240	#define CONFIG_LOOPW 1 /* enable loopw command */
	241	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	242	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	243
	244	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
acea76a2 WD	245
	246	/*-----------------------------------------------------------------------
	247	* PCI stuff
	248	*-----------------------------------------------------------------------
	249	*/
	250	/* General PCI */
	251	#define CONFIG_PCI /* include pci support */
	252	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	253	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	254	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
	255
	256	/* Board-specific PCI */
	257	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
	258	#define CFG_PCI_TARGET_INIT /* let board init pci target */
	259
8a316c9b	260	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
acea76a2 WD	261	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	262
	263	/*
	264	* For booting Linux, the board info and command line data
	265	* have to be in the first 8 MB of memory, since this is
	266	* the maximum mapped by the Linux kernel during initialization.
	267	*/
	268	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	269	/*-----------------------------------------------------------------------
	270	* Cache Configuration
	271	*/
	272	#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
	273	#define CFG_CACHELINE_SIZE 32 /* ... */
	274	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	275	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	276	#endif
	277
	278	/*
	279	* Internal Definitions
	280	*
	281	* Boot Flags
	282	*/
	283	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	284	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	285
	286	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	287	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	288	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	289	#endif
	290	#endif /* __CONFIG_H */