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3cbeb0f0 EB |
1 | /* |
2 | * Copyright (C) 2014 Eukréa Electromatique | |
3 | * Author: Eric Bénard <eric@eukrea.com> | |
4 | * | |
5 | * Configuration settings for the Embest RIoTboard | |
6 | * | |
7 | * based on mx6*sabre*.h which are : | |
8 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef __RIOTBOARD_CONFIG_H | |
14 | #define __RIOTBOARD_CONFIG_H | |
15 | ||
3cbeb0f0 | 16 | #define CONFIG_MXC_UART_BASE UART2_BASE |
12ca05a3 | 17 | #define CONSOLE_DEV "ttymxc1" |
3cbeb0f0 EB |
18 | |
19 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
20 | ||
1368f993 | 21 | #define CONFIG_IMX_THERMAL |
3cbeb0f0 EB |
22 | |
23 | /* Size of malloc() pool */ | |
24 | #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) | |
25 | ||
3cbeb0f0 EB |
26 | #define CONFIG_MXC_UART |
27 | ||
3cbeb0f0 | 28 | /* I2C Configs */ |
3cbeb0f0 EB |
29 | #define CONFIG_SYS_I2C |
30 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
31 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
32 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 33 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
3cbeb0f0 EB |
34 | #define CONFIG_SYS_I2C_SPEED 100000 |
35 | ||
36 | /* USB Configs */ | |
3cbeb0f0 EB |
37 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
38 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
39 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
40 | #define CONFIG_MXC_USB_FLAGS 0 | |
41 | ||
42 | /* MMC Configs */ | |
3cbeb0f0 EB |
43 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
44 | ||
3cbeb0f0 EB |
45 | #define CONFIG_FEC_MXC |
46 | #define CONFIG_MII | |
47 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
48 | #define CONFIG_FEC_XCV_TYPE RGMII | |
49 | #define CONFIG_ETHPRIME "FEC" | |
50 | #define CONFIG_FEC_MXC_PHYADDR 4 | |
51 | ||
3cbeb0f0 EB |
52 | #define CONFIG_PHY_ATHEROS |
53 | ||
3cbeb0f0 | 54 | #ifdef CONFIG_CMD_SF |
3cbeb0f0 EB |
55 | #define CONFIG_MXC_SPI |
56 | #define CONFIG_SF_DEFAULT_BUS 0 | |
155fa9af | 57 | #define CONFIG_SF_DEFAULT_CS 0 |
3cbeb0f0 EB |
58 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
59 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
60 | #endif | |
61 | ||
3cbeb0f0 EB |
62 | #define CONFIG_ARP_TIMEOUT 200UL |
63 | ||
3cbeb0f0 EB |
64 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
65 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
66 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
67 | ||
3cbeb0f0 EB |
68 | /* Physical Memory Map */ |
69 | #define CONFIG_NR_DRAM_BANKS 1 | |
70 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
71 | ||
72 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
73 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
74 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
75 | ||
76 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
77 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
78 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
79 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
80 | ||
056845c2 | 81 | /* Environment organization */ |
3cbeb0f0 EB |
82 | #define CONFIG_ENV_SIZE (8 * 1024) |
83 | ||
84 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
85 | /* RiOTboard */ | |
c86efd85 | 86 | #define CONFIG_FDTFILE "imx6dl-riotboard.dtb" |
3cbeb0f0 EB |
87 | #define CONFIG_SYS_FSL_USDHC_NUM 3 |
88 | #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ | |
89 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
90 | #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ | |
91 | #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
92 | /* MarSBoard */ | |
c86efd85 | 93 | #define CONFIG_FDTFILE "imx6q-marsboard.dtb" |
3cbeb0f0 EB |
94 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
95 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
96 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) | |
97 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
98 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
99 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
100 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
101 | #endif | |
102 | ||
3cbeb0f0 | 103 | /* Framebuffer */ |
3cbeb0f0 | 104 | #define CONFIG_VIDEO_IPUV3 |
3cbeb0f0 EB |
105 | #define CONFIG_VIDEO_BMP_RLE8 |
106 | #define CONFIG_SPLASH_SCREEN | |
107 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
108 | #define CONFIG_BMP_16BPP | |
109 | #define CONFIG_VIDEO_LOGO | |
110 | #define CONFIG_VIDEO_BMP_LOGO | |
3cbeb0f0 EB |
111 | #define CONFIG_IMX_HDMI |
112 | #define CONFIG_IMX_VIDEO_SKIP | |
113 | ||
729d2a34 | 114 | #include <config_distro_defaults.h> |
e51c1e8e | 115 | #include "mx6_common.h" |
729d2a34 | 116 | |
c86efd85 IP |
117 | /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
118 | * 1M script, 1M pxe and the ramdisk at the end */ | |
119 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
120 | "bootm_size=0x10000000\0" \ | |
121 | "kernel_addr_r=0x12000000\0" \ | |
122 | "fdt_addr_r=0x13000000\0" \ | |
123 | "scriptaddr=0x13100000\0" \ | |
124 | "pxefile_addr_r=0x13200000\0" \ | |
125 | "ramdisk_addr_r=0x13300000\0" | |
126 | ||
127 | #define BOOT_TARGET_DEVICES(func) \ | |
128 | func(MMC, mmc, 0) \ | |
129 | func(MMC, mmc, 1) \ | |
130 | func(MMC, mmc, 2) \ | |
131 | func(USB, usb, 0) \ | |
132 | func(PXE, pxe, na) \ | |
133 | func(DHCP, dhcp, na) | |
134 | ||
135 | #include <config_distro_bootcmd.h> | |
136 | ||
137 | #define CONSOLE_STDIN_SETTINGS \ | |
138 | "stdin=serial\0" | |
139 | ||
140 | #define CONSOLE_STDOUT_SETTINGS \ | |
141 | "stdout=serial\0" \ | |
142 | "stderr=serial\0" | |
143 | ||
144 | #define CONSOLE_ENV_SETTINGS \ | |
145 | CONSOLE_STDIN_SETTINGS \ | |
146 | CONSOLE_STDOUT_SETTINGS | |
147 | ||
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
149 | CONSOLE_ENV_SETTINGS \ | |
150 | MEM_LAYOUT_ENV_SETTINGS \ | |
151 | "fdtfile=" CONFIG_FDTFILE "\0" \ | |
0f29a61c | 152 | "finduuid=part uuid mmc 0:1 uuid\0" \ |
c86efd85 IP |
153 | BOOTENV |
154 | ||
3cbeb0f0 | 155 | #endif /* __RIOTBOARD_CONFIG_H */ |