[people/ms/u-boot.git] / include / configs / ep8248.h

/*
 * Copyright (C) 2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * U-Boot configuration for Embedded Planet EP8248 boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC8248
#define CPU_ID_STR		"MPC8248"

#define CONFIG_EP8248			/* Embedded Planet EP8248 board */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

#define CONFIG_SYS_BCSR		0xFA000000

/* Pass open firmware flat device tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_TBCLK        (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH  "/soc/cpm/serial <at> 11a80"

/* Select ethernet configuration */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#define CONFIG_NET_MULTI
#define CONFIG_SYS_CPMFCR_RAMTYPE	0
#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#define CONFIG_HAS_ETH0
#define CONFIG_ETHER_ON_FCC1		1
/* - Rx clock is CLK10
 * - Tx clock is CLK11
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)

#define CONFIG_HAS_ETH1
#define CONFIG_ETHER_ON_FCC2		1
/* - Rx clock is CLK13
 * - Tx clock is CLK14
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		0	/* Not used - implemented in BCSR */

#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)

#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE

#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD

#define MIIDELAY		udelay(1)

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm FF860000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_SYS_FLASH_BASE		0xFF800000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define	CONFIG_SYS_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
#define CONFIG_SYS_JFFS_CUSTOM_PART
#endif

#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
#endif

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */

#define CONFIG_SYS_DEFAULT_IMMR	0x00010000

#define CONFIG_SYS_IMMR		0xF0000000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot                  */

#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CONFIG_SYS_HID2		0

#define CONFIG_SYS_SIUMCR		0x01240200
#define CONFIG_SYS_SYPCR		0xFFFF0683
#define CONFIG_SYS_BCR			0x00000000
#define CONFIG_SYS_SCCR		SCCR_DFBRG01

#define CONFIG_SYS_RMR			RMR_CSRE
#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CONFIG_SYS_RCCR		0

#define CONFIG_SYS_MPTPR		0x1300
#define CONFIG_SYS_PSDMR		0x82672522
#define CONFIG_SYS_PSRT		0x4B

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00001841)
#define CONFIG_SYS_SDRAM_OR		0xFF0030C0

#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
#define CONFIG_SYS_OR0_PRELIM		0xFF8008C2
#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
#define CONFIG_SYS_OR2_PRELIM		0xFFF00864

#define CONFIG_SYS_RESET_ADDRESS	0xC0000000

#endif /* __CONFIG_H */
Commit	Line	Data
f901a83b WD	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Embedded Planet EP8248 boards.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#define CONFIG_MPC8248
	30	#define CPU_ID_STR "MPC8248"
	31
	32	#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
	33
f901a83b WD	34	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	35
	36	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	37	#define CONFIG_ENV_OVERWRITE
	38
	39	/*
	40	* Select serial console configuration
	41	*
	42	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	43	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	44	* for SCC).
	45	*/
	46	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	47	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	48	#undef CONFIG_CONS_NONE /* It's not on external UART */
	49	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	50
6d0f6bcf	51	#define CONFIG_SYS_BCSR 0xFA000000
f901a83b	52
45f89f34 MZ	53	/* Pass open firmware flat device tree */
	54	#define CONFIG_OF_LIBFDT 1
	55	#define CONFIG_OF_BOARD_SETUP 1
	56
	57	#define OF_TBCLK (bd->bi_busfreq / 4)
	58	#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
	59
	60	/* Select ethernet configuration */
f901a83b WD	61	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	62	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	63	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	64
45f89f34 MZ	65	#define CONFIG_NET_MULTI
	66	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
	67	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
f901a83b	68
45f89f34 MZ	69	#define CONFIG_HAS_ETH0
45f89f34 MZ	70	#define CONFIG_ETHER_ON_FCC1 1
f901a83b WD	71	/* - Rx clock is CLK10
	72	* - Tx clock is CLK11
	73	* - BDs/buffers on 60x bus
	74	* - Full duplex
	75	*/
45f89f34 MZ	76	#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
45f89f34 MZ	77	#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 \| CMXFCR_TF1CS_CLK11)
f901a83b	78
45f89f34 MZ	79	#define CONFIG_HAS_ETH1
45f89f34 MZ	80	#define CONFIG_ETHER_ON_FCC2 1
f901a83b WD	81	/* - Rx clock is CLK13
	82	* - Tx clock is CLK14
	83	* - BDs/buffers on 60x bus
	84	* - Full duplex
	85	*/
45f89f34 MZ	86	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
45f89f34 MZ	87	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
f901a83b WD	88
	89	#define CONFIG_MII /* MII PHY management */
	90	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	91	/*
	92	* GPIO pins used for bit-banged MII communications
	93	*/
	94	#define MDIO_PORT 0 /* Not used - implemented in BCSR */
be225442	95
6d0f6bcf JCPV	96	#define MDIO_ACTIVE ((vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFB)
	97	#define MDIO_TRISTATE ((vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x04)
	98	#define MDIO_READ ((vu_char )(CONFIG_SYS_BCSR + 8) & 1)
f901a83b	99
6d0f6bcf JCPV	100	#define MDIO(bit) if(bit) (vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x01; \
6d0f6bcf JCPV	101	else (vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFE
f901a83b	102
6d0f6bcf JCPV	103	#define MDC(bit) if(bit) (vu_char )(CONFIG_SYS_BCSR + 8) \|= 0x02; \
6d0f6bcf JCPV	104	else (vu_char )(CONFIG_SYS_BCSR + 8) &= 0xFD
f901a83b WD	105
	106	#define MIIDELAY udelay(1)
	107
f901a83b WD	108	#ifndef CONFIG_8260_CLKIN
	109	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	110	#endif
	111
	112	#define CONFIG_BAUDRATE 38400
	113
1bec3d30	114
80ff4f99 JL	115	/*
	116	* BOOTP options
	117	*/
	118	#define CONFIG_BOOTP_BOOTFILESIZE
	119	#define CONFIG_BOOTP_BOOTPATH
	120	#define CONFIG_BOOTP_GATEWAY
	121	#define CONFIG_BOOTP_HOSTNAME
	122
	123
1bec3d30 JL	124	/*
	125	* Command line configuration.
	126	*/
	127	#include <config_cmd_default.h>
	128
	129	#define CONFIG_CMD_DHCP
	130	#define CONFIG_CMD_ECHO
	131	#define CONFIG_CMD_I2C
	132	#define CONFIG_CMD_IMMAP
	133	#define CONFIG_CMD_MII
	134	#define CONFIG_CMD_PING
	135
f901a83b WD	136
	137	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	138	#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
	139	#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
	140
1bec3d30	141	#if defined(CONFIG_CMD_KGDB)
f901a83b WD	142	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	143	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	144	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	145	#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
	146	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	147	#endif
	148
	149	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	150	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	151
	152	/*
	153	* Miscellaneous configurable options
	154	*/
6d0f6bcf JCPV	155	#define CONFIG_SYS_HUSH_PARSER
	156	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	157	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	158	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
1bec3d30	159	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	160	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
f901a83b	161	#else
6d0f6bcf	162	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
f901a83b	163	#endif
6d0f6bcf JCPV	164	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	165	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	166	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
f901a83b	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	169	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
f901a83b	170
6d0f6bcf	171	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
f901a83b	172
6d0f6bcf	173	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
f901a83b	174
6d0f6bcf	175	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
f901a83b	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_BASE 0xFF800000
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_CFI
00b1883a	179	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	180	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
6d0f6bcf JCPV	181	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
f901a83b	182
6d0f6bcf	183	#define CONFIG_SYS_DIRECT_FLASH_TFTP
f901a83b	184
1bec3d30	185	#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf JCPV	186	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	187	#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
	188	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
	189	#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
	190	#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
	191	#define CONFIG_SYS_JFFS_CUSTOM_PART
80ff4f99	192	#endif
f901a83b	193
1bec3d30	194	#if defined(CONFIG_CMD_I2C)
f901a83b	195	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
6d0f6bcf JCPV	196	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
6d0f6bcf JCPV	197	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
80ff4f99	198	#endif
f901a83b	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	201	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	202	#define CONFIG_SYS_RAMBOOT
f901a83b WD	203	#endif
f901a83b WD	204
6d0f6bcf	205	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
f901a83b	206
5a1aceb0	207	#define CONFIG_ENV_IS_IN_FLASH
f901a83b	208
5a1aceb0	209	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	210	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	211	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
5a1aceb0	212	#endif /* CONFIG_ENV_IS_IN_FLASH */
f901a83b	213
6d0f6bcf	214	#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
f901a83b	215
6d0f6bcf	216	#define CONFIG_SYS_IMMR 0xF0000000
f901a83b	217
6d0f6bcf JCPV	218	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	219	#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	220	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	221	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	222	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
f901a83b WD	223
f901a83b WD	224	/* Hard reset configuration word */
6d0f6bcf	225	#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
f901a83b	226	/* No slaves */
6d0f6bcf JCPV	227	#define CONFIG_SYS_HRCW_SLAVE1 0
	228	#define CONFIG_SYS_HRCW_SLAVE2 0
	229	#define CONFIG_SYS_HRCW_SLAVE3 0
	230	#define CONFIG_SYS_HRCW_SLAVE4 0
	231	#define CONFIG_SYS_HRCW_SLAVE5 0
	232	#define CONFIG_SYS_HRCW_SLAVE6 0
	233	#define CONFIG_SYS_HRCW_SLAVE7 0
f901a83b WD	234
	235	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	236	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
6d0f6bcf JCPV	239	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
f901a83b	240
6d0f6bcf	241	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
1bec3d30	242	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	243	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
f901a83b WD	244	#endif
f901a83b WD	245
6d0f6bcf JCPV	246	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	247	#define CONFIG_SYS_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
f901a83b	248
6d0f6bcf	249	#define CONFIG_SYS_HID2 0
f901a83b	250
6d0f6bcf JCPV	251	#define CONFIG_SYS_SIUMCR 0x01240200
	252	#define CONFIG_SYS_SYPCR 0xFFFF0683
	253	#define CONFIG_SYS_BCR 0x00000000
	254	#define CONFIG_SYS_SCCR SCCR_DFBRG01
f901a83b	255
6d0f6bcf JCPV	256	#define CONFIG_SYS_RMR RMR_CSRE
	257	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	258	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	259	#define CONFIG_SYS_RCCR 0
f901a83b	260
6d0f6bcf JCPV	261	#define CONFIG_SYS_MPTPR 0x1300
	262	#define CONFIG_SYS_PSDMR 0x82672522
	263	#define CONFIG_SYS_PSRT 0x4B
f901a83b	264
6d0f6bcf JCPV	265	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	266	#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE \| 0x00001841)
	267	#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
f901a83b	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| 0x00001801)
	270	#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
	271	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR \| 0x00000801)
	272	#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
f901a83b	273
6d0f6bcf	274	#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
f901a83b WD	275
f901a83b WD	276	#endif /* __CONFIG_H */