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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG | |
4 | * | |
5 | * This file is based on similar values for other boards found in other | |
6 | * U-Boot config files, and some that I found in the EP8260 manual. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
a562e1bd | 29 | * |
9dd611b8 | 30 | * "EP8260 H, V.1.1" |
53677ef1 WD |
31 | * - 64M 60x Bus SDRAM |
32 | * - 32M Local Bus SDRAM | |
33 | * - 16M Flash (4 x AM29DL323DB90WDI) | |
34 | * - 128k NVRAM with RTC | |
9dd611b8 | 35 | * |
6d0f6bcf | 36 | * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2) |
53677ef1 WD |
37 | * - 300MHz/133MHz/66MHz |
38 | * - 64M 60x Bus SDRAM | |
39 | * - 32M Local Bus SDRAM | |
40 | * - 32M Flash | |
41 | * - 128k NVRAM with RTC | |
5b1d7137 WD |
42 | */ |
43 | ||
44 | #ifndef __CONFIG_H | |
45 | #define __CONFIG_H | |
46 | ||
9dd611b8 | 47 | /* Define this to enable support the EP8260 H2 version */ |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_EP8260_H2 1 |
49 | /* #undef CONFIG_SYS_EP8260_H2 */ | |
9dd611b8 | 50 | |
9c4c5ae3 JL |
51 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
52 | ||
5b1d7137 WD |
53 | /* What is the oscillator's (UX2) frequency in Hz? */ |
54 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
55 | ||
56 | /*----------------------------------------------------------------------- | |
57 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
58 | *----------------------------------------------------------------------- | |
59 | * What should MODCK_H be? It is dependent on the oscillator | |
60 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
61 | * Here are some example values (all frequencies are in MHz): | |
62 | * | |
63 | * MODCK_H MODCK[1-3] Osc CPM Core | |
64 | * ------- ---------- --- --- ---- | |
65 | * 0x2 0x2 33 133 133 | |
66 | * 0x2 0x3 33 133 166 | |
67 | * 0x2 0x4 33 133 200 | |
68 | * 0x2 0x5 33 133 233 | |
69 | * 0x2 0x6 33 133 266 | |
70 | * | |
71 | * 0x5 0x5 66 133 133 | |
72 | * 0x5 0x6 66 133 166 | |
73 | * 0x5 0x7 66 133 200 * | |
74 | * 0x6 0x0 66 133 233 | |
75 | * 0x6 0x1 66 133 266 | |
76 | * 0x6 0x2 66 133 300 | |
77 | */ | |
6d0f6bcf JCPV |
78 | #ifdef CONFIG_SYS_EP8260_H2 |
79 | #define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) | |
9dd611b8 | 80 | #else |
6d0f6bcf | 81 | #define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) |
9dd611b8 | 82 | #endif |
5b1d7137 WD |
83 | |
84 | /* Define this if you want to boot from 0x00000100. If you don't define | |
85 | * this, you will need to program the bootloader to 0xfff00000, and | |
86 | * get the hardware reset config words at 0xfe000000. The simplest | |
87 | * way to do that is to program the bootloader at both addresses. | |
88 | * It is suggested that you just let U-Boot live at 0x00000000. | |
89 | */ | |
6d0f6bcf JCPV |
90 | /* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */ |
91 | /* #undef CONFIG_SYS_SBC_BOOT_LOW */ | |
5b1d7137 WD |
92 | |
93 | /* The reset command will not work as expected if the reset address does | |
94 | * not point to the correct address. | |
95 | */ | |
96 | ||
6d0f6bcf | 97 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
5b1d7137 WD |
98 | |
99 | /* What should the base address of the main FLASH be and how big is | |
100 | * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk | |
101 | * The main FLASH is whichever is connected to *CS0. U-Boot expects | |
102 | * this to be the SIMM. | |
103 | */ | |
6d0f6bcf JCPV |
104 | #ifdef CONFIG_SYS_EP8260_H2 |
105 | #define CONFIG_SYS_FLASH0_BASE 0xFE000000 | |
106 | #define CONFIG_SYS_FLASH0_SIZE 32 | |
9dd611b8 | 107 | #else |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_FLASH0_BASE 0xFF000000 |
109 | #define CONFIG_SYS_FLASH0_SIZE 16 | |
9dd611b8 | 110 | #endif |
5b1d7137 WD |
111 | |
112 | /* What should the base address of the secondary FLASH be and how big | |
113 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
114 | * to *CS6. U-Boot expects this to be the on board FLASH. If you don't | |
115 | * want it enabled, don't define these constants. | |
116 | */ | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_FLASH1_BASE 0 |
118 | #define CONFIG_SYS_FLASH1_SIZE 0 | |
119 | #undef CONFIG_SYS_FLASH1_BASE | |
120 | #undef CONFIG_SYS_FLASH1_SIZE | |
5b1d7137 WD |
121 | |
122 | /* What should be the base address of SDRAM DIMM (60x bus) and how big is | |
123 | * it (in Mbytes)? | |
124 | */ | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
126 | #define CONFIG_SYS_SDRAM0_SIZE 64 | |
5b1d7137 | 127 | |
6d0f6bcf | 128 | /* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the |
5b1d7137 WD |
129 | * local bus (8260 local bus is NOT cacheable!) |
130 | */ | |
6d0f6bcf JCPV |
131 | /* #define CONFIG_SYS_LSDRAM */ |
132 | #undef CONFIG_SYS_LSDRAM | |
5b1d7137 | 133 | |
6d0f6bcf | 134 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 WD |
135 | /* What should be the base address of SDRAM DIMM (local bus) and how big is |
136 | * it (in Mbytes)? | |
137 | */ | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_SDRAM1_BASE 0x04000000 |
139 | #define CONFIG_SYS_SDRAM1_SIZE 32 | |
5b1d7137 | 140 | #else |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_SDRAM1_BASE 0 |
142 | #define CONFIG_SYS_SDRAM1_SIZE 0 | |
143 | #undef CONFIG_SYS_SDRAM1_BASE | |
144 | #undef CONFIG_SYS_SDRAM1_SIZE | |
145 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
146 | |
147 | /* What should be the base address of NVRAM and how big is | |
148 | * it (in Bytes) | |
149 | */ | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 |
151 | #define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 | |
5b1d7137 WD |
152 | |
153 | /* The RTC is a Dallas DS1556 | |
154 | */ | |
155 | #define CONFIG_RTC_DS1556 | |
156 | ||
157 | /* What should be the base address of the LEDs and switch S0? | |
158 | * If you don't want them enabled, don't define this. | |
159 | */ | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_LED_BASE 0x00000000 |
161 | #undef CONFIG_SYS_LED_BASE | |
5b1d7137 WD |
162 | |
163 | /* | |
164 | * select serial console configuration | |
165 | * | |
166 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
167 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
168 | * for SCC). | |
169 | * | |
170 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
171 | * defined elsewhere. | |
172 | */ | |
173 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
174 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
175 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
176 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
177 | ||
178 | /* | |
179 | * select ethernet configuration | |
180 | * | |
181 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
182 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
183 | * for FCC) | |
184 | * | |
185 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 186 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
5b1d7137 WD |
187 | */ |
188 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
189 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
190 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
191 | #define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ | |
192 | ||
193 | #if ( CONFIG_ETHER_INDEX == 3 ) | |
194 | ||
195 | /* | |
196 | * - Rx-CLK is CLK15 | |
197 | * - Tx-CLK is CLK16 | |
198 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
199 | * - Enable Half Duplex in FSMR | |
200 | */ | |
6d0f6bcf JCPV |
201 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
202 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
5b1d7137 WD |
203 | |
204 | /* | |
205 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
206 | */ | |
6d0f6bcf JCPV |
207 | #ifdef CONFIG_SYS_LSDRAM |
208 | #define CONFIG_SYS_CPMFCR_RAMTYPE 3 | |
209 | #else /* CONFIG_SYS_LSDRAM */ | |
210 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
211 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
212 | |
213 | /* - Enable Half Duplex in FSMR */ | |
6d0f6bcf JCPV |
214 | /* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ |
215 | # define CONFIG_SYS_FCC_PSMR 0 | |
5b1d7137 WD |
216 | |
217 | #else /* CONFIG_ETHER_INDEX */ | |
218 | # error "on EP8260 ethernet must be FCC3" | |
219 | #endif /* CONFIG_ETHER_INDEX */ | |
220 | ||
221 | /* | |
222 | * select i2c support configuration | |
223 | * | |
224 | * Supported configurations are {none, software, hardware} drivers. | |
225 | * If the software driver is chosen, there are some additional | |
226 | * configuration items that the driver uses to drive the port pins. | |
227 | */ | |
228 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
229 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
231 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
5b1d7137 WD |
232 | |
233 | /* | |
234 | * Software (bit-bang) I2C driver configuration | |
235 | */ | |
236 | #ifdef CONFIG_SOFT_I2C | |
237 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
238 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
239 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
240 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
241 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
242 | else iop->pdat &= ~0x00010000 | |
243 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
244 | else iop->pdat &= ~0x00020000 | |
245 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
246 | #endif /* CONFIG_SOFT_I2C */ | |
247 | ||
248 | /* #define CONFIG_RTC_DS174x */ | |
249 | ||
250 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
251 | * environment variables. Otherwise, the environment will be | |
252 | * put in the same sector as U-Boot, and changing variables | |
253 | * will erase U-Boot temporarily | |
254 | */ | |
0e8d1586 | 255 | #define CONFIG_ENV_IN_OWN_SECT |
5b1d7137 WD |
256 | |
257 | /* Define to allow the user to overwrite serial and ethaddr */ | |
258 | #define CONFIG_ENV_OVERWRITE | |
259 | ||
260 | /* What should the console's baud rate be? */ | |
6d0f6bcf | 261 | #ifdef CONFIG_SYS_EP8260_H2 |
9dd611b8 WD |
262 | #define CONFIG_BAUDRATE 9600 |
263 | #else | |
a562e1bd | 264 | #define CONFIG_BAUDRATE 115200 |
9dd611b8 | 265 | #endif |
5b1d7137 WD |
266 | |
267 | /* Ethernet MAC address */ | |
268 | #define CONFIG_ETHADDR 00:10:EC:00:30:8C | |
269 | ||
270 | #define CONFIG_IPADDR 192.168.254.130 | |
271 | #define CONFIG_SERVERIP 192.168.254.49 | |
272 | ||
273 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
274 | #define CONFIG_BOOTDELAY -1 | |
275 | ||
276 | /* undef this to save memory */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_LONGHELP |
5b1d7137 WD |
278 | |
279 | /* Monitor Command Prompt */ | |
6d0f6bcf | 280 | #define CONFIG_SYS_PROMPT "=> " |
5b1d7137 WD |
281 | |
282 | /* Define this variable to enable the "hush" shell (from | |
283 | Busybox) as command line interpreter, thus enabling | |
284 | powerful command line syntax like | |
285 | if...then...else...fi conditionals or `&&' and '||' | |
286 | constructs ("shell scripts"). | |
287 | If undefined, you get the old, much simpler behaviour | |
288 | with a somewhat smapper memory footprint. | |
289 | */ | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_HUSH_PARSER |
291 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
5b1d7137 | 292 | |
1bec3d30 | 293 | |
80ff4f99 JL |
294 | /* |
295 | * BOOTP options | |
296 | */ | |
297 | #define CONFIG_BOOTP_BOOTFILESIZE | |
298 | #define CONFIG_BOOTP_BOOTPATH | |
299 | #define CONFIG_BOOTP_GATEWAY | |
300 | #define CONFIG_BOOTP_HOSTNAME | |
301 | ||
302 | ||
5b1d7137 | 303 | /* |
1bec3d30 JL |
304 | * Command line configuration. |
305 | */ | |
4e620410 JCPV |
306 | #include <config_cmd_default.h> |
307 | ||
308 | #define CONFIG_CMD_ASKENV | |
309 | #define CONFIG_CMD_BEDBUG | |
310 | #define CONFIG_CMD_CACHE | |
311 | #define CONFIG_CMD_CDP | |
312 | #define CONFIG_CMD_DATE | |
313 | #define CONFIG_CMD_DIAG | |
314 | #define CONFIG_CMD_ELF | |
315 | #define CONFIG_CMD_FAT | |
316 | #define CONFIG_CMD_I2C | |
317 | #define CONFIG_CMD_IMMAP | |
318 | #define CONFIG_CMD_IRQ | |
319 | #define CONFIG_CMD_PING | |
320 | #define CONFIG_CMD_PORTIO | |
321 | #define CONFIG_CMD_REGINFO | |
322 | #define CONFIG_CMD_SAVES | |
323 | #define CONFIG_CMD_SDRAM | |
324 | #define CONFIG_CMD_SNTP | |
1bec3d30 | 325 | |
1bec3d30 | 326 | #undef CONFIG_CMD_DCR |
1bec3d30 | 327 | #undef CONFIG_CMD_XIMG |
5b1d7137 WD |
328 | |
329 | /* Where do the internal registers live? */ | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_IMMR 0xF0000000 |
331 | #define CONFIG_SYS_DEFAULT_IMMR 0x00010000 | |
5b1d7137 WD |
332 | |
333 | /* Where do the on board registers (CS4) live? */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_REGS_BASE 0xFA000000 |
5b1d7137 WD |
335 | |
336 | /***************************************************************************** | |
337 | * | |
338 | * You should not have to modify any of the following settings | |
339 | * | |
340 | *****************************************************************************/ | |
341 | ||
342 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
343 | #define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ | |
344 | ||
c837dcb1 | 345 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
5b1d7137 | 346 | |
5b1d7137 WD |
347 | /* |
348 | * Miscellaneous configurable options | |
349 | */ | |
1bec3d30 | 350 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 351 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5b1d7137 | 352 | #else |
6d0f6bcf | 353 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5b1d7137 WD |
354 | #endif |
355 | ||
356 | /* Print Buffer Size */ | |
6d0f6bcf | 357 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
5b1d7137 | 358 | |
6d0f6bcf | 359 | #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ |
5b1d7137 | 360 | |
6d0f6bcf | 361 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
5b1d7137 | 362 | |
6d0f6bcf JCPV |
363 | #ifdef CONFIG_SYS_LSDRAM |
364 | #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ | |
365 | #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ | |
5b1d7137 | 366 | #else |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
368 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ | |
369 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
370 | |
371 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
372 | ||
6d0f6bcf JCPV |
373 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
374 | #define CONFIG_SYS_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */ | |
5b1d7137 | 375 | |
6d0f6bcf | 376 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
5b1d7137 WD |
377 | |
378 | /* valid baudrates */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
5b1d7137 WD |
380 | |
381 | /* | |
382 | * Low Level Configuration Settings | |
383 | * (address mappings, register initial values, etc.) | |
384 | * You should know what you are doing if you make changes here. | |
385 | */ | |
386 | ||
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
388 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
5b1d7137 WD |
389 | |
390 | /*----------------------------------------------------------------------- | |
391 | * Hard Reset Configuration Words | |
392 | */ | |
393 | ||
6d0f6bcf JCPV |
394 | #if defined(CONFIG_SYS_SBC_BOOT_LOW) |
395 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
5b1d7137 | 396 | #else |
6d0f6bcf JCPV |
397 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000) |
398 | #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ | |
5b1d7137 | 399 | |
6d0f6bcf JCPV |
400 | #ifdef CONFIG_SYS_EP8260_H2 |
401 | /* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */ | |
402 | #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\ | |
403 | ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\ | |
404 | ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) ) | |
5b1d7137 | 405 | |
6d0f6bcf | 406 | #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\ |
8bde7f77 | 407 | HRCW_L2CPC01 |\ |
6d0f6bcf | 408 | CONFIG_SYS_SBC_HRCW_IMMR |\ |
5b1d7137 WD |
409 | HRCW_APPC10 |\ |
410 | HRCW_CS10PC01 |\ | |
6d0f6bcf JCPV |
411 | CONFIG_SYS_SBC_MODCK_H |\ |
412 | CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) | |
9dd611b8 | 413 | #else |
6d0f6bcf | 414 | #define CONFIG_SYS_HRCW_MASTER 0x10400245 |
9dd611b8 | 415 | #endif |
5b1d7137 WD |
416 | |
417 | /* no slaves */ | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
419 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
420 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
421 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
422 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
423 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
424 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
5b1d7137 WD |
425 | |
426 | /*----------------------------------------------------------------------- | |
427 | * Definitions for initial stack pointer and data area (in DPRAM) | |
428 | */ | |
6d0f6bcf JCPV |
429 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
430 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
431 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ | |
432 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
433 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
5b1d7137 WD |
434 | |
435 | /*----------------------------------------------------------------------- | |
436 | * Start addresses for the final memory configuration | |
437 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
438 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
439 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
5b1d7137 | 440 | */ |
6d0f6bcf | 441 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
5b1d7137 WD |
442 | |
443 | ||
6d0f6bcf JCPV |
444 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
445 | # define CONFIG_SYS_RAMBOOT | |
5b1d7137 WD |
446 | #endif |
447 | ||
6d0f6bcf JCPV |
448 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
449 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
5b1d7137 WD |
450 | |
451 | /* | |
452 | * For booting Linux, the board info and command line data | |
453 | * have to be in the first 8 MB of memory, since this is | |
454 | * the maximum mapped by the Linux kernel during initialization. | |
455 | */ | |
6d0f6bcf | 456 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5b1d7137 WD |
457 | |
458 | /*----------------------------------------------------------------------- | |
459 | * FLASH and environment organization | |
460 | */ | |
6d0f6bcf JCPV |
461 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
462 | #ifdef CONFIG_SYS_EP8260_H2 | |
463 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
9dd611b8 | 464 | #else |
6d0f6bcf | 465 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
9dd611b8 | 466 | #endif |
5b1d7137 | 467 | |
6d0f6bcf JCPV |
468 | #ifdef CONFIG_SYS_EP8260_H2 |
469 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ | |
470 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
bd51626c | 471 | #else |
6d0f6bcf JCPV |
472 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
473 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
bd51626c | 474 | #endif |
5b1d7137 | 475 | |
6d0f6bcf | 476 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 477 | # define CONFIG_ENV_IS_IN_FLASH 1 |
5b1d7137 | 478 | |
0e8d1586 | 479 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 480 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 | 481 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
5b1d7137 | 482 | # else |
6d0f6bcf | 483 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
484 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
485 | # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
486 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
5b1d7137 | 487 | #else |
9314cee6 | 488 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 489 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 490 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 491 | #endif /* CONFIG_SYS_RAMBOOT */ |
5b1d7137 WD |
492 | |
493 | /*----------------------------------------------------------------------- | |
494 | * Cache Configuration | |
495 | */ | |
6d0f6bcf | 496 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
5b1d7137 | 497 | |
1bec3d30 | 498 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 499 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5b1d7137 WD |
500 | #endif |
501 | ||
502 | /*----------------------------------------------------------------------- | |
503 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
504 | *----------------------------------------------------------------------- | |
505 | * HID0 also contains cache control - initially enable both caches and | |
506 | * invalidate contents, then the final state leaves only the instruction | |
507 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
508 | * but Soft reset does not. | |
509 | * | |
510 | * HID1 has only read-only information - nothing to set. | |
511 | */ | |
6d0f6bcf | 512 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
5b1d7137 WD |
513 | HID0_DCE |\ |
514 | HID0_ICFI |\ | |
515 | HID0_DCI |\ | |
516 | HID0_IFEM |\ | |
517 | HID0_ABE) | |
6d0f6bcf | 518 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 | 519 | /* 8260 local bus is NOT cacheable */ |
6d0f6bcf | 520 | #define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ |
5b1d7137 WD |
521 | HID0_IFEM |\ |
522 | HID0_ABE |\ | |
523 | HID0_EMCP) | |
6d0f6bcf JCPV |
524 | #else /* !CONFIG_SYS_LSDRAM */ |
525 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ | |
5b1d7137 WD |
526 | HID0_IFEM |\ |
527 | HID0_ABE |\ | |
528 | HID0_EMCP) | |
6d0f6bcf | 529 | #endif /* CONFIG_SYS_LSDRAM */ |
5b1d7137 | 530 | |
6d0f6bcf | 531 | #define CONFIG_SYS_HID2 0 |
5b1d7137 WD |
532 | |
533 | /*----------------------------------------------------------------------- | |
534 | * RMR - Reset Mode Register | |
535 | *----------------------------------------------------------------------- | |
536 | */ | |
6d0f6bcf | 537 | #define CONFIG_SYS_RMR 0 |
5b1d7137 WD |
538 | |
539 | /*----------------------------------------------------------------------- | |
540 | * BCR - Bus Configuration 4-25 | |
541 | *----------------------------------------------------------------------- | |
542 | */ | |
6d0f6bcf | 543 | #define CONFIG_SYS_BCR (BCR_EBM |\ |
5b1d7137 WD |
544 | BCR_PLDP |\ |
545 | BCR_EAV |\ | |
9dd611b8 WD |
546 | BCR_NPQM0) |
547 | ||
5b1d7137 WD |
548 | /*----------------------------------------------------------------------- |
549 | * SIUMCR - SIU Module Configuration 4-31 | |
550 | *----------------------------------------------------------------------- | |
551 | */ | |
6d0f6bcf | 552 | #define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ |
8bde7f77 WD |
553 | SIUMCR_APPC10 |\ |
554 | SIUMCR_CS10PC01) | |
5b1d7137 | 555 | |
5b1d7137 WD |
556 | /*----------------------------------------------------------------------- |
557 | * SYPCR - System Protection Control 11-9 | |
558 | * SYPCR can only be written once after reset! | |
559 | *----------------------------------------------------------------------- | |
560 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
561 | */ | |
6d0f6bcf | 562 | #ifdef CONFIG_SYS_EP8260_H2 |
a562e1bd WD |
563 | /* TBD: Find out why setting the BMT to 0xff causes the FCC to |
564 | * generate TX buffer underrun errors for large packets under | |
565 | * Linux | |
9dd611b8 | 566 | */ |
6d0f6bcf | 567 | #define CONFIG_SYS_SYPCR_BMT 0x00000600 |
9dd611b8 | 568 | #else |
6d0f6bcf | 569 | #define CONFIG_SYS_SYPCR_BMT SYPCR_BMT |
9dd611b8 WD |
570 | #endif |
571 | ||
6d0f6bcf JCPV |
572 | #ifdef CONFIG_SYS_LSDRAM |
573 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ | |
574 | CONFIG_SYS_SYPCR_BMT |\ | |
8bde7f77 WD |
575 | SYPCR_PBME |\ |
576 | SYPCR_LBME |\ | |
577 | SYPCR_SWP) | |
5b1d7137 | 578 | #else |
6d0f6bcf JCPV |
579 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
580 | CONFIG_SYS_SYPCR_BMT |\ | |
8bde7f77 WD |
581 | SYPCR_PBME |\ |
582 | SYPCR_SWP) | |
5b1d7137 | 583 | #endif |
9dd611b8 | 584 | |
5b1d7137 WD |
585 | /*----------------------------------------------------------------------- |
586 | * TMCNTSC - Time Counter Status and Control 4-40 | |
587 | *----------------------------------------------------------------------- | |
588 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
589 | * and enable Time Counter | |
590 | */ | |
6d0f6bcf | 591 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
8bde7f77 WD |
592 | TMCNTSC_ALR |\ |
593 | TMCNTSC_TCF |\ | |
594 | TMCNTSC_TCE) | |
5b1d7137 WD |
595 | |
596 | /*----------------------------------------------------------------------- | |
597 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
598 | *----------------------------------------------------------------------- | |
599 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
600 | * Periodic timer | |
601 | */ | |
6d0f6bcf JCPV |
602 | #ifdef CONFIG_SYS_EP8260_H2 |
603 | #define CONFIG_SYS_PISCR (PISCR_PS |\ | |
8bde7f77 | 604 | PISCR_PTF |\ |
9dd611b8 WD |
605 | PISCR_PTE) |
606 | #else | |
6d0f6bcf | 607 | #define CONFIG_SYS_PISCR 0 |
9dd611b8 WD |
608 | #endif |
609 | ||
5b1d7137 WD |
610 | /*----------------------------------------------------------------------- |
611 | * SCCR - System Clock Control 9-8 | |
612 | *----------------------------------------------------------------------- | |
613 | */ | |
6d0f6bcf JCPV |
614 | #ifdef CONFIG_SYS_EP8260_H2 |
615 | #define CONFIG_SYS_SCCR (SCCR_DFBRG00) | |
bd51626c | 616 | #else |
6d0f6bcf | 617 | #define CONFIG_SYS_SCCR (SCCR_DFBRG01) |
bd51626c | 618 | #endif |
5b1d7137 WD |
619 | |
620 | /*----------------------------------------------------------------------- | |
621 | * RCCR - RISC Controller Configuration 13-7 | |
622 | *----------------------------------------------------------------------- | |
623 | */ | |
6d0f6bcf | 624 | #define CONFIG_SYS_RCCR 0 |
5b1d7137 WD |
625 | |
626 | /*----------------------------------------------------------------------- | |
627 | * MPTPR - Memory Refresh Timer Prescale Register 10-32 | |
628 | *----------------------------------------------------------------------- | |
629 | */ | |
6d0f6bcf | 630 | #define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK) |
5b1d7137 WD |
631 | |
632 | /* | |
633 | * Init Memory Controller: | |
634 | * | |
635 | * Bank Bus Machine PortSz Device | |
636 | * ---- --- ------- ------ ------ | |
637 | * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) | |
638 | * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) | |
639 | * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) | |
640 | * 3 unused | |
641 | * 4 60x GPCM 8 bit Board Regs, NVRTC | |
642 | * 5 unused | |
643 | * 6 unused | |
644 | * 7 unused | |
645 | * 8 PCMCIA | |
646 | * 9 unused | |
647 | * 10 unused | |
648 | * 11 unused | |
649 | */ | |
650 | ||
651 | /*----------------------------------------------------------------------- | |
652 | * BRx - Base Register | |
653 | * Ref: Section 10.3.1 on page 10-14 | |
654 | * ORx - Option Register | |
655 | * Ref: Section 10.3.2 on page 10-18 | |
656 | *----------------------------------------------------------------------- | |
657 | */ | |
658 | ||
659 | /* Bank 0 - FLASH | |
660 | * | |
661 | */ | |
6d0f6bcf | 662 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
8bde7f77 | 663 | BRx_PS_64 |\ |
5b1d7137 | 664 | BRx_DECC_NONE |\ |
8bde7f77 WD |
665 | BRx_MS_GPCM_P |\ |
666 | BRx_V) | |
5b1d7137 | 667 | |
6d0f6bcf | 668 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
8bde7f77 WD |
669 | ORxG_CSNT |\ |
670 | ORxG_ACS_DIV1 |\ | |
9dd611b8 | 671 | ORxG_SCY_8_CLK |\ |
8bde7f77 | 672 | ORxG_EHTR) |
5b1d7137 WD |
673 | |
674 | /* Bank 1 - SDRAM | |
675 | * PSDRAM | |
676 | */ | |
6d0f6bcf | 677 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
678 | BRx_PS_64 |\ |
679 | BRx_MS_SDRAM_P |\ | |
680 | BRx_V) | |
5b1d7137 | 681 | |
6d0f6bcf | 682 | #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ |
8bde7f77 WD |
683 | ORxS_BPD_4 |\ |
684 | ORxS_ROWST_PBI1_A6 |\ | |
685 | ORxS_NUMR_12) | |
5b1d7137 | 686 | |
6d0f6bcf JCPV |
687 | #ifdef CONFIG_SYS_EP8260_H2 |
688 | #define CONFIG_SYS_PSDMR 0xC34E246E | |
9dd611b8 | 689 | #else |
6d0f6bcf | 690 | #define CONFIG_SYS_PSDMR 0xC34E2462 |
9dd611b8 | 691 | #endif |
5b1d7137 | 692 | |
6d0f6bcf | 693 | #define CONFIG_SYS_PSRT 0x64 |
5b1d7137 | 694 | |
6d0f6bcf | 695 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 WD |
696 | /* Bank 2 - SDRAM |
697 | * LSDRAM | |
698 | */ | |
699 | ||
6d0f6bcf | 700 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
701 | BRx_PS_32 |\ |
702 | BRx_MS_SDRAM_L |\ | |
703 | BRx_V) | |
5b1d7137 | 704 | |
6d0f6bcf | 705 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ |
8bde7f77 WD |
706 | ORxS_BPD_4 |\ |
707 | ORxS_ROWST_PBI0_A9 |\ | |
708 | ORxS_NUMR_12) | |
5b1d7137 | 709 | |
6d0f6bcf JCPV |
710 | #define CONFIG_SYS_LSDMR 0x416A2562 |
711 | #define CONFIG_SYS_LSRT 0x64 | |
5b1d7137 | 712 | #else |
6d0f6bcf JCPV |
713 | #define CONFIG_SYS_LSRT 0x0 |
714 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
715 | |
716 | /* Bank 4 - On board registers | |
717 | * NVRTC and BCSR | |
718 | */ | |
6d0f6bcf | 719 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
720 | BRx_PS_8 |\ |
721 | BRx_MS_GPCM_P |\ | |
722 | BRx_V) | |
5b1d7137 | 723 | /* |
6d0f6bcf | 724 | #define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ |
8bde7f77 WD |
725 | ORxG_CSNT |\ |
726 | ORxG_ACS_DIV1 |\ | |
727 | ORxG_SCY_10_CLK |\ | |
728 | ORxG_TRLX) | |
5b1d7137 | 729 | */ |
6d0f6bcf | 730 | #define CONFIG_SYS_OR4_PRELIM 0xfff00854 |
5b1d7137 | 731 | |
9dd611b8 | 732 | #ifdef _NOT_USED_SINCE_NOT_WORKING_ |
5b1d7137 WD |
733 | /* Bank 8 - On board registers |
734 | * PCMCIA (currently not working!) | |
735 | */ | |
6d0f6bcf | 736 | #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
737 | BRx_PS_16 |\ |
738 | BRx_MS_GPCM_P |\ | |
739 | BRx_V) | |
5b1d7137 | 740 | |
6d0f6bcf | 741 | #define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\ |
8bde7f77 WD |
742 | ORxG_CSNT |\ |
743 | ORxG_ACS_DIV1 |\ | |
5b1d7137 | 744 | ORxG_SETA |\ |
8bde7f77 | 745 | ORxG_SCY_10_CLK) |
9dd611b8 | 746 | #endif |
5b1d7137 WD |
747 | |
748 | /* | |
749 | * Internal Definitions | |
750 | * | |
751 | * Boot Flags | |
752 | */ | |
753 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
754 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
755 | ||
700a0c64 WD |
756 | /* |
757 | * JFFS2 partitions | |
758 | * | |
759 | */ | |
760 | /* No command line, one static partition, whole device */ | |
68d7d651 | 761 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
762 | #define CONFIG_JFFS2_DEV "nor0" |
763 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
764 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
765 | ||
766 | /* mtdparts command line support */ | |
767 | /* Note: fake mtd_id used, no linux mtd map file */ | |
768 | /* | |
68d7d651 | 769 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
770 | #define MTDIDS_DEFAULT "" |
771 | #define MTDPARTS_DEFAULT "" | |
772 | */ | |
773 | ||
5b1d7137 | 774 | #endif /* __CONFIG_H */ |