[people/ms/u-boot.git] / include / configs / espt.h

/*
 * Configuation settings for the ESPT-GIGA board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ESPT_H
#define __ESPT_H

#define CONFIG_CPU_SH7763	1
#define CONFIG_ESPT	1
#define __LITTLE_ENDIAN		1

/*
 * Command line configuration.
 */
#define CONFIG_CMD_SDRAM

#define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE    1

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SCIF */
#define CONFIG_SCIF_CONSOLE		1
#define CONFIG_CONS_SCIF0		1

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
#define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
								passed to kernel */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
												settings for this board */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Flash(NOR) S29JL064H */
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  (150)

/* U-Boot setting */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))

/* Clock */
#define CONFIG_SYS_CLK_FREQ	66666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV      4

/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#endif /* __SH7763RDP_H */
Commit	Line	Data
74d9c16a NI	1	/*
	2	* Configuation settings for the ESPT-GIGA board
	3	*
	4	* Copyright (C) 2008 Renesas Solutions Corp.
	5	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
74d9c16a NI	8	*/
	9
	10	#ifndef __ESPT_H
	11	#define __ESPT_H
	12
74d9c16a NI	13	#define CONFIG_CPU_SH7763 1
	14	#define CONFIG_ESPT 1
	15	#define __LITTLE_ENDIAN 1
	16
	17	/*
	18	* Command line configuration.
	19	*/
	20	#define CONFIG_CMD_SDRAM
74d9c16a	21
74d9c16a NI	22	#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
	23	#define CONFIG_ENV_OVERWRITE 1
	24
18a40e84	25	#define CONFIG_DISPLAY_BOARDINFO
74d9c16a NI	26	#undef CONFIG_SHOW_BOOT_PROGRESS
	27
	28	/* SCIF */
	29	#define CONFIG_SCIF_CONSOLE 1
74d9c16a NI	30	#define CONFIG_CONS_SCIF0 1
74d9c16a NI	31
54fbf475	32	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
74d9c16a	33	#define CONFIG_SYS_LONGHELP /* undef to save memory */
74d9c16a NI	34	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	35	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	36	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
	37	#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
	38	passed to kernel */
	39	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
	40	settings for this board */
	41
	42	/* SDRAM */
	43	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	44	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	45	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	46	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
	47
	48	/* Flash(NOR) S29JL064H */
	49	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	50	#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
	51	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	52	#define CONFIG_SYS_MAX_FLASH_SECT (150)
	53
a187559e	54	/* U-Boot setting */
74d9c16a NI	55	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	56	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	57	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	58	/* Size of DRAM reserved for malloc() use */
	59	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
74d9c16a NI	60	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	61
	62	#define CONFIG_SYS_FLASH_CFI
	63	#define CONFIG_FLASH_CFI_DRIVER
	64	#undef CONFIG_SYS_FLASH_QUIET_TEST
	65	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	66	/* Timeout for Flash erase operations (in ms) */
	67	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	68	/* Timeout for Flash write operations (in ms) */
	69	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	70	/* Timeout for Flash set sector lock bit operations (in ms) */
	71	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	72	/* Timeout for Flash clear lock bit operations (in ms) */
	73	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	74	/* Use hardware flash sectors protection instead of U-Boot software protection */
	75	#undef CONFIG_SYS_FLASH_PROTECTION
	76	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
	77	#define CONFIG_ENV_IS_IN_FLASH
	78	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	79	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	80	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
	81	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	82	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	83	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	84	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	85
	86	/* Clock */
	87	#define CONFIG_SYS_CLK_FREQ 66666666
684a501e NI	88	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	89	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
74d9c16a	90	#define CONFIG_SYS_TMU_CLK_DIV 4
74d9c16a NI	91
74d9c16a NI	92	/* Ether */
74d9c16a NI	93	#define CONFIG_SH_ETHER 1
	94	#define CONFIG_SH_ETHER_USE_PORT (1)
	95	#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
25a028bb YS	96	#define CONFIG_PHYLIB
	97	#define CONFIG_BITBANGMII
	98	#define CONFIG_BITBANGMII_MULTI
a80a6619	99	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
74d9c16a NI	100
74d9c16a NI	101	#endif /* __SH7763RDP_H */