[thirdparty/u-boot.git] / include / configs / espt.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the ESPT-GIGA board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 */

#ifndef __ESPT_H
#define __ESPT_H

#define CONFIG_CPU_SH7763	1
#define __LITTLE_ENDIAN		1

#define CONFIG_ENV_OVERWRITE    1

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SCIF */
#define CONFIG_CONS_SCIF0		1

#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
												settings for this board */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Flash(NOR) S29JL064H */
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  (150)

/* U-Boot setting */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))

/* Clock */
#define CONFIG_SYS_CLK_FREQ	66666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV      4

/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#endif /* __SH7763RDP_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
74d9c16a NI	2	/*
	3	* Configuation settings for the ESPT-GIGA board
	4	*
	5	* Copyright (C) 2008 Renesas Solutions Corp.
	6	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
74d9c16a NI	7	*/
	8
	9	#ifndef __ESPT_H
	10	#define __ESPT_H
	11
74d9c16a	12	#define CONFIG_CPU_SH7763 1
74d9c16a NI	13	#define __LITTLE_ENDIAN 1
74d9c16a NI	14
74d9c16a NI	15	#define CONFIG_ENV_OVERWRITE 1
74d9c16a NI	16
18a40e84	17	#define CONFIG_DISPLAY_BOARDINFO
74d9c16a NI	18	#undef CONFIG_SHOW_BOOT_PROGRESS
	19
	20	/* SCIF */
74d9c16a NI	21	#define CONFIG_CONS_SCIF0 1
74d9c16a NI	22
74d9c16a	23	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
74d9c16a NI	24	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
	25	settings for this board */
	26
	27	/* SDRAM */
	28	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	29	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	30	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	31	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
	32
	33	/* Flash(NOR) S29JL064H */
	34	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	35	#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
	36	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	37	#define CONFIG_SYS_MAX_FLASH_SECT (150)
	38
a187559e	39	/* U-Boot setting */
74d9c16a NI	40	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	41	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	42	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	43	/* Size of DRAM reserved for malloc() use */
	44	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
74d9c16a NI	45	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	46
	47	#define CONFIG_SYS_FLASH_CFI
	48	#define CONFIG_FLASH_CFI_DRIVER
	49	#undef CONFIG_SYS_FLASH_QUIET_TEST
	50	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	51	/* Timeout for Flash erase operations (in ms) */
	52	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	53	/* Timeout for Flash write operations (in ms) */
	54	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	55	/* Timeout for Flash set sector lock bit operations (in ms) */
	56	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	57	/* Timeout for Flash clear lock bit operations (in ms) */
	58	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	59	/* Use hardware flash sectors protection instead of U-Boot software protection */
	60	#undef CONFIG_SYS_FLASH_PROTECTION
	61	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
74d9c16a NI	62	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	63	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	64	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
	65	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	66	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	67	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	68	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	69
	70	/* Clock */
	71	#define CONFIG_SYS_CLK_FREQ 66666666
684a501e NI	72	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	73	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
74d9c16a	74	#define CONFIG_SYS_TMU_CLK_DIV 4
74d9c16a NI	75
74d9c16a NI	76	/* Ether */
74d9c16a NI	77	#define CONFIG_SH_ETHER_USE_PORT (1)
74d9c16a NI	78	#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
25a028bb YS	79	#define CONFIG_BITBANGMII
25a028bb YS	80	#define CONFIG_BITBANGMII_MULTI
a80a6619	81	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
74d9c16a NI	82
74d9c16a NI	83	#endif /* __SH7763RDP_H */