[thirdparty/u-boot.git] / include / configs / ethernut5.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011
 * egnite GmbH <info@egnite.de>
 *
 * Configuation settings for Ethernut 5 with AT91SAM9XE.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/hardware.h>

/* The first stage boot loader expects u-boot running at this address. */

/* The first stage boot loader takes care of low level initialization. */
#define CONFIG_SKIP_LOWLEVEL_INIT

/* Set our official architecture number. */
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5

/* CPU information */
#define CONFIG_ARCH_CPU_INIT

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */

/* 32kB internal SRAM */
#define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
#define CONFIG_SRAM_SIZE	(32 << 10)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
				GENERATED_GBL_DATA_SIZE)

/* 128MB SDRAM in 1 bank */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE \
					- CONFIG_SYS_MALLOC_LEN)

/* 512kB on-chip NOR flash */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
# define CONFIG_AT91_EFLASH
# define CONFIG_SYS_MAX_FLASH_SECT	32
# define CONFIG_SYS_FLASH_PROTECTION	/* First stage loader in sector 0 */
# define CONFIG_EFLASH_PROTSECTORS	1


/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET	0x3DE000
#define CONFIG_ENV_SIZE		(132 << 10)
#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_MAX_HZ	15000000

#ifndef MINIMAL_LOADER
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_NAND_ATMEL
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
#endif

/* JFFS2 */
#ifdef CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_NAND
#endif

/* Ethernet */
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_PHY_ID			0
#define CONFIG_MACB_SEARCH_PHY

/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"host"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#endif

/* RTC */
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51
#endif

/* I2C */
#define CONFIG_SYS_MAX_I2C_BUS	1

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	100000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0

#define I2C_SOFT_DECLARATIONS

#define GPIO_I2C_SCL		AT91_PIO_PORTA, 24
#define GPIO_I2C_SDA		AT91_PIO_PORTA, 23

#define I2C_INIT { \
	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
}

#define I2C_ACTIVE	at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
#define I2C_TRISTATE	at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_SDA(bit)	at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
#define I2C_DELAY	udelay(100)
#define I2C_READ	at91_get_pio_value(AT91_PIO_PORTA, 23)

/* DHCP/BOOTP options */
#ifdef CONFIG_CMD_DHCP
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_SYS_AUTOLOAD	"n"
#endif

/* File systems */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS

/* Boot command */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTCOMMAND	"sf probe 0:0; " \
				"sf read 0x22000000 0xc6000 0x294000; " \
				"bootm 0x22000000"

/* Misc. u-boot settings */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
14c32614 TS	2	/*
	3	* (C) Copyright 2011
	4	* egnite GmbH <info@egnite.de>
	5	*
	6	* Configuation settings for Ethernut 5 with AT91SAM9XE.
14c32614 TS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/hardware.h>
	13
	14	/* The first stage boot loader expects u-boot running at this address. */
14c32614 TS	15
	16	/* The first stage boot loader takes care of low level initialization. */
	17	#define CONFIG_SKIP_LOWLEVEL_INIT
	18
	19	/* Set our official architecture number. */
14c32614 TS	20	#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
	21
	22	/* CPU information */
14c32614 TS	23	#define CONFIG_ARCH_CPU_INIT
	24
	25	/* ARM asynchronous clock */
	26	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
	27	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
14c32614 TS	28
	29	/* 32kB internal SRAM */
	30	#define CONFIG_SRAM_BASE 0x00300000 /AT91SAM9XE_SRAM_BASE /
	31	#define CONFIG_SRAM_SIZE (32 << 10)
3d6ba91e RH	32	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
3d6ba91e RH	33	GENERATED_GBL_DATA_SIZE)
14c32614 TS	34
	35	/* 128MB SDRAM in 1 bank */
	36	#define CONFIG_NR_DRAM_BANKS 1
	37	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	38	#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
	39	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
	40	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	42	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	43	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
	44	- CONFIG_SYS_MALLOC_LEN)
	45
	46	/* 512kB on-chip NOR flash */
	47	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	48	# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
	49	# define CONFIG_AT91_EFLASH
	50	# define CONFIG_SYS_MAX_FLASH_SECT 32
	51	# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
	52	# define CONFIG_EFLASH_PROTSECTORS 1
	53
94db5120 WY	54
	55	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
	56	#define CONFIG_ENV_OFFSET 0x3DE000
	57	#define CONFIG_ENV_SIZE (132 << 10)
	58	#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
	59	#define CONFIG_ENV_SPI_MAX_HZ 15000000
14c32614	60
ef0f2f57	61	#ifndef MINIMAL_LOADER
14c32614 TS	62	#endif
	63
	64	/* NAND flash */
	65	#ifdef CONFIG_CMD_NAND
	66	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	67	#define CONFIG_SYS_NAND_BASE 0x40000000
	68	#define CONFIG_SYS_NAND_DBW_8
	69	#define CONFIG_NAND_ATMEL
	70	/* our ALE is AD21 */
	71	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	72	/* our CLE is AD22 */
	73	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
ac45bb16	74	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
14c32614 TS	75	#endif
	76
	77	/* JFFS2 */
	78	#ifdef CONFIG_CMD_JFFS2
14c32614 TS	79	#define CONFIG_JFFS2_CMDLINE
	80	#define CONFIG_JFFS2_NAND
	81	#endif
	82
	83	/* Ethernet */
14c32614 TS	84	#define CONFIG_NET_RETRY_COUNT 20
	85	#define CONFIG_MACB
	86	#define CONFIG_RMII
	87	#define CONFIG_PHY_ID 0
	88	#define CONFIG_MACB_SEARCH_PHY
	89
	90	/* MMC */
	91	#ifdef CONFIG_CMD_MMC
14c32614 TS	92	#define CONFIG_GENERIC_ATMEL_MCI
	93	#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
	94	#endif
	95
	96	/* USB */
	97	#ifdef CONFIG_CMD_USB
	98	#define CONFIG_USB_ATMEL
dcd2f1a0	99	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
14c32614 TS	100	#define CONFIG_USB_OHCI_NEW
	101	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	102	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
	103	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
	104	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
14c32614 TS	105	#endif
	106
	107	/* RTC */
	108	#if defined(CONFIG_CMD_DATE) \|\| defined(CONFIG_CMD_SNTP)
	109	#define CONFIG_RTC_PCF8563
	110	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	111	#endif
	112
	113	/* I2C */
	114	#define CONFIG_SYS_MAX_I2C_BUS 1
14c32614	115
ea818dbb HS	116	#define CONFIG_SYS_I2C
	117	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	118	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
	119	#define CONFIG_SYS_I2C_SOFT_SLAVE 0
	120
14c32614 TS	121	#define I2C_SOFT_DECLARATIONS
	122
	123	#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
	124	#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
	125
	126	#define I2C_INIT { \
	127	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
	128	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	129	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
	130	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
	131	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
	132	}
	133
	134	#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
	135	#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
	136	#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
	137	#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
	138	#define I2C_DELAY udelay(100)
	139	#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
	140
	141	/* DHCP/BOOTP options */
	142	#ifdef CONFIG_CMD_DHCP
	143	#define CONFIG_BOOTP_BOOTFILESIZE
14c32614 TS	144	#define CONFIG_SYS_AUTOLOAD "n"
	145	#endif
	146
	147	/* File systems */
	148	#define CONFIG_MTD_DEVICE
	149	#define CONFIG_MTD_PARTITIONS
14c32614 TS	150
14c32614 TS	151	/* Boot command */
14c32614 TS	152	#define CONFIG_CMDLINE_TAG
	153	#define CONFIG_SETUP_MEMORY_TAGS
	154	#define CONFIG_INITRD_TAG
94db5120 WY	155	#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
	156	"sf read 0x22000000 0xc6000 0x294000; " \
	157	"bootm 0x22000000"
14c32614 TS	158
14c32614 TS	159	/* Misc. u-boot settings */
14c32614 TS	160
14c32614 TS	161	#endif