]>
Commit | Line | Data |
---|---|---|
39539887 WD |
1 | /* |
2 | * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) | |
3 | * Curt Brune <curt@cucy.com> | |
4 | * | |
5 | * Configuation settings for evb4510 board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * If we are developing, we might want to start u-boot from ram | |
31 | * so we MUST NOT initialize critical regs like mem-timing ... | |
32 | * | |
33 | * Also swap the flash1 and flash2 addresses during debug. | |
34 | * | |
8aa1a2d1 | 35 | * #define CONFIG_SKIP_LOWLEVEL_INIT |
39539887 | 36 | */ |
39539887 WD |
37 | |
38 | /* | |
39 | * High Level Configuration Options | |
40 | * (easy to change) | |
41 | */ | |
42 | #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ | |
43 | #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ | |
44 | #define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ | |
45 | #define CONFIG_EVB4510 1 /* on an EVB4510 Board */ | |
46 | ||
a1f4a3dd WD |
47 | #define CONFIG_USE_IRQ |
48 | #define CONFIG_STACKSIZE_IRQ (4*1024) | |
49 | #define CONFIG_STACKSIZE_FIQ (4*1024) | |
39539887 WD |
50 | |
51 | /* | |
52 | * Size of malloc() pool | |
53 | */ | |
6d0f6bcf JCPV |
54 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
55 | #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
39539887 WD |
56 | |
57 | /* | |
58 | * Hardware drivers | |
59 | */ | |
60 | #define CONFIG_DRIVER_S3C4510_ETH 1 | |
61 | #define CONFIG_DRIVER_S3C4510_I2C 1 | |
62 | #define CONFIG_DRIVER_S3C4510_UART 1 | |
63 | #define CONFIG_DRIVER_S3C4510_FLASH 1 | |
64 | ||
65 | /* | |
66 | * select serial console configuration | |
67 | */ | |
a1f4a3dd | 68 | #define CONFIG_SERIAL1 1 /* we use Serial line 1, could also use 2 */ |
39539887 WD |
69 | |
70 | /* allow to overwrite serial and ethaddr */ | |
71 | #define CONFIG_ENV_OVERWRITE | |
72 | ||
73 | #define CONFIG_BAUDRATE 19200 | |
74 | ||
2fd90ce5 JL |
75 | /* |
76 | * BOOTP options | |
77 | */ | |
78 | #define CONFIG_BOOTP_SUBNETMASK | |
79 | #define CONFIG_BOOTP_GATEWAY | |
80 | #define CONFIG_BOOTP_HOSTNAME | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_BOOTFILESIZE | |
39539887 | 83 | |
39539887 | 84 | |
1bec3d30 JL |
85 | /* |
86 | * Command line configuration. | |
87 | */ | |
88 | #include <config_cmd_default.h> | |
89 | ||
90 | #define CONFIG_CMD_PING | |
91 | ||
92 | ||
39539887 WD |
93 | #define CONFIG_ETHADDR 00:40:95:36:35:33 |
94 | #define CONFIG_NETMASK 255.255.255.0 | |
95 | #define CONFIG_IPADDR 10.0.0.11 | |
96 | #define CONFIG_SERVERIP 10.0.0.1 | |
97 | #define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ | |
98 | ||
a1f4a3dd WD |
99 | #define CONFIG_BOOTDELAY 2 |
100 | #define CONFIG_BOOTCOMMAND "tftp 100000 uImage" | |
53677ef1 | 101 | /* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ |
39539887 | 102 | |
1bec3d30 | 103 | #if defined(CONFIG_CMD_KGDB) |
39539887 WD |
104 | #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ |
105 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
106 | #endif | |
107 | ||
108 | /* | |
109 | * Miscellaneous configurable options | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
112 | #define CONFIG_SYS_PROMPT "evb4510 # " /* Monitor Command Prompt */ | |
113 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
39539887 | 117 | |
a1f4a3dd WD |
118 | #define CONFIG_CMDLINE_TAG /* allow passing of command line args to linux */ |
119 | #define CONFIG_SETUP_MEMORY_TAGS | |
120 | #define CONFIG_INITRD_TAG | |
121 | ||
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
123 | #define CONFIG_SYS_MEMTEST_END 0x00780000 /* 4 ... 8 MB in DRAM */ | |
39539887 | 124 | |
6d0f6bcf | 125 | #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
39539887 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_LOAD_ADDR 0x00000000 /* default load address */ |
39539887 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_SYS_CLK_FREQ 50000000 /* CPU freq: 50 MHz */ |
130 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 KHz */ | |
39539887 WD |
131 | |
132 | /* valid baudrates */ | |
6d0f6bcf | 133 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
39539887 WD |
134 | |
135 | /*----------------------------------------------------------------------- | |
136 | * Stack sizes | |
137 | * | |
138 | * The stack sizes are set up in start.S using the settings below | |
139 | */ | |
140 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
141 | #ifdef CONFIG_USE_IRQ | |
142 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
143 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
144 | #endif | |
145 | ||
146 | /*----------------------------------------------------------------------- | |
147 | * Physical Memory Map after relocation | |
148 | */ | |
149 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ | |
150 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
151 | #define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ | |
152 | ||
153 | #define PHYS_FLASH_1 0x01000000 /* Flash Bank #1 */ | |
154 | #define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip, 8bit access) */ | |
155 | ||
156 | #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ | |
157 | #define PHYS_FLASH_2_SIZE 0x00080000 /* 512KB (one chip, 8bit access) */ | |
158 | ||
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
160 | #define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_1_SIZE | |
39539887 WD |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * FLASH and environment organization | |
164 | */ | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ | |
167 | #define CONFIG_SYS_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ | |
39539887 WD |
168 | |
169 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_FLASH_ERASE_TOUT (4*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
171 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
39539887 WD |
172 | |
173 | /* environment settings */ | |
5a1aceb0 | 174 | #define CONFIG_ENV_IS_IN_FLASH |
93f6d725 | 175 | #undef CONFIG_ENV_IS_NOWHERE |
39539887 | 176 | |
6d0f6bcf | 177 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) /* environment start address */ |
0e8d1586 JCPV |
178 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
179 | #define CONFIG_ENV_SIZE 0x1000 /* max size for environment */ | |
39539887 WD |
180 | |
181 | #endif /* __CONFIG_H */ |