projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 76dd9b6a RS |
1 | /* |
| 2 | * Copyright (C) 2013 Samsung Electronics | |
| 3 | * | |
| 4 | * Configuration settings for the SAMSUNG EXYNOS5 board. | |
| 5 | * | |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 12 | /* High Level Configuration Options */ | |
| 13 | #define CONFIG_SAMSUNG /* in a SAMSUNG core */ | |
| 14 | #define CONFIG_S5P /* S5P Family */ | |
| 15 | #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ | |
| 16 | ||
| 17 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
| 18 | ||
| 19 | #define CONFIG_SYS_GENERIC_BOARD | |
| 20 | #define CONFIG_ARCH_CPU_INIT | |
| 21 | #define CONFIG_DISPLAY_CPUINFO | |
| 22 | #define CONFIG_DISPLAY_BOARDINFO | |
| 23 | #define CONFIG_BOARD_COMMON | |
| 24 | #define CONFIG_ARCH_EARLY_INIT_R | |
| 25 | #define CONFIG_EXYNOS_SPL | |
| 26 | ||
| 76dd9b6a RS |
27 | /* Allow tracing to be enabled */ |
| 28 | #define CONFIG_TRACE | |
| 29 | #define CONFIG_CMD_TRACE | |
| 30 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
| 31 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
| 32 | #define CONFIG_TRACE_EARLY | |
| 33 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
| 34 | ||
| 35 | /* Keep L2 Cache Disabled */ | |
| 36 | #define CONFIG_SYS_DCACHE_OFF | |
| 37 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
| 38 | ||
| 39 | /* Enable ACE acceleration for SHA1 and SHA256 */ | |
| 40 | #define CONFIG_EXYNOS_ACE_SHA | |
| 41 | #define CONFIG_SHA_HW_ACCEL | |
| 42 | ||
| 43 | /* input clock of PLL: SMDK5250 has 24MHz input clock */ | |
| 44 | #define CONFIG_SYS_CLK_FREQ 24000000 | |
| 45 | ||
| 46 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 47 | #define CONFIG_CMDLINE_TAG | |
| 48 | #define CONFIG_INITRD_TAG | |
| 49 | #define CONFIG_CMDLINE_EDITING | |
| 50 | ||
| 51 | /* Power Down Modes */ | |
| 52 | #define S5P_CHECK_SLEEP 0x00000BAD | |
| 53 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
| 54 | #define S5P_CHECK_LPA 0xABAD0000 | |
| 55 | ||
| 56 | /* Offset for inform registers */ | |
| 57 | #define INFORM0_OFFSET 0x800 | |
| 58 | #define INFORM1_OFFSET 0x804 | |
| 59 | #define INFORM2_OFFSET 0x808 | |
| 60 | #define INFORM3_OFFSET 0x80c | |
| 61 | ||
| 62 | /* Size of malloc() pool */ | |
| 63 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) | |
| 64 | ||
| 65 | /* select serial console configuration */ | |
| 66 | #define CONFIG_BAUDRATE 115200 | |
| 67 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 | |
| 68 | #define CONFIG_SILENT_CONSOLE | |
| 69 | ||
| 70 | /* Enable keyboard */ | |
| 71 | #define CONFIG_CROS_EC /* CROS_EC protocol */ | |
| 72 | #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ | |
| 73 | #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ | |
| 74 | #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ | |
| 75 | #define CONFIG_CMD_CROS_EC | |
| 76 | #define CONFIG_KEYBOARD | |
| 77 | ||
| 78 | /* Console configuration */ | |
| 79 | #define CONFIG_CONSOLE_MUX | |
| 80 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 81 | #define EXYNOS_DEVICE_SETTINGS \ | |
| 82 | "stdin=serial,cros-ec-keyb\0" \ | |
| 83 | "stdout=serial,lcd\0" \ | |
| 84 | "stderr=serial,lcd\0" | |
| 85 | ||
| 86 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 87 | EXYNOS_DEVICE_SETTINGS | |
| 88 | ||
| 89 | /* SD/MMC configuration */ | |
| 90 | #define CONFIG_GENERIC_MMC | |
| 91 | #define CONFIG_MMC | |
| 92 | #define CONFIG_SDHCI | |
| 93 | #define CONFIG_S5P_SDHCI | |
| 94 | #define CONFIG_DWMMC | |
| 95 | #define CONFIG_EXYNOS_DWMMC | |
| 96 | #define CONFIG_SUPPORT_EMMC_BOOT | |
| 7f673c99 | 97 | #define CONFIG_BOUNCE_BUFFER |
| 76dd9b6a RS |
98 | |
| 99 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 100 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 101 | ||
| 102 | /* PWM */ | |
| 103 | #define CONFIG_PWM | |
| 104 | ||
| 105 | /* allow to overwrite serial and ethaddr */ | |
| 106 | #define CONFIG_ENV_OVERWRITE | |
| 107 | ||
| 108 | /* Command definition*/ | |
| 109 | #include <config_cmd_default.h> | |
| 110 | ||
| 111 | #define CONFIG_CMD_PING | |
| 112 | #define CONFIG_CMD_ELF | |
| 113 | #define CONFIG_CMD_MMC | |
| 114 | #define CONFIG_CMD_EXT2 | |
| 115 | #define CONFIG_CMD_FAT | |
| 116 | #define CONFIG_CMD_NET | |
| 117 | #define CONFIG_CMD_HASH | |
| 118 | ||
| 119 | #define CONFIG_BOOTDELAY 3 | |
| 120 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 121 | ||
| 122 | /* Thermal Management Unit */ | |
| 123 | #define CONFIG_EXYNOS_TMU | |
| 124 | #define CONFIG_CMD_DTT | |
| 125 | #define CONFIG_TMU_CMD_DTT | |
| 126 | ||
| 127 | /* TPM */ | |
| 128 | #define CONFIG_TPM | |
| 129 | #define CONFIG_CMD_TPM | |
| 130 | #define CONFIG_TPM_TIS_I2C | |
| 131 | #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 | |
| 132 | #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 | |
| 133 | ||
| 134 | /* MMC SPL */ | |
| 76dd9b6a RS |
135 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
| 136 | ||
| 137 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 138 | #define CONFIG_SPL_GPIO_SUPPORT | |
| 139 | ||
| 140 | /* specific .lds file */ | |
| 141 | #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" | |
| 76dd9b6a RS |
142 | |
| 143 | /* Miscellaneous configurable options */ | |
| 144 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 145 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
| 146 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 147 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
| 148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 149 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" | |
| 150 | /* Boot Argument Buffer Size */ | |
| 151 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 152 | /* memtest works on */ | |
| 153 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
| 154 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
| 155 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
| 156 | ||
| 157 | #define CONFIG_RD_LVL | |
| 158 | ||
| 76dd9b6a RS |
159 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
| 160 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
| 161 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
| 162 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
| 163 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
| 164 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
| 165 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
| 166 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
| 167 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
| 168 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
| 169 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
| 170 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
| 171 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
| 172 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
| 173 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
| 174 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
| 175 | ||
| 176 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
| 177 | ||
| 178 | /* FLASH and environment organization */ | |
| 179 | #define CONFIG_SYS_NO_FLASH | |
| 180 | #undef CONFIG_CMD_IMLS | |
| 181 | ||
| 182 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 183 | ||
| 184 | #define CONFIG_SECURE_BL1_ONLY | |
| 185 | ||
| 186 | /* Secure FW size configuration */ | |
| 187 | #ifdef CONFIG_SECURE_BL1_ONLY | |
| 188 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
| 189 | #else | |
| 190 | #define CONFIG_SEC_FW_SIZE 0 | |
| 191 | #endif | |
| 192 | ||
| 193 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
| 194 | #define CONFIG_RES_BLOCK_SIZE (512) | |
| 195 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
| 196 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
| 197 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
| 198 | ||
| 199 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
| 200 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
| fa253157 AS |
201 | |
| 202 | /* Store environment at the end of a 4 MB SPI flash */ | |
| 203 | #define FLASH_SIZE (0x4 << 20) | |
| 204 | #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) | |
| 76dd9b6a RS |
205 | |
| 206 | /* U-boot copy size from boot Media to DRAM.*/ | |
| 207 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) | |
| 208 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
| 209 | ||
| 210 | #define CONFIG_SPI_BOOTING | |
| 211 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 | |
| 212 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) | |
| 213 | ||
| 214 | #define CONFIG_DOS_PARTITION | |
| 215 | #define CONFIG_EFI_PARTITION | |
| 216 | #define CONFIG_CMD_PART | |
| 217 | #define CONFIG_PARTITION_UUIDS | |
| 218 | ||
| 219 | /* I2C */ | |
| 220 | #define CONFIG_SYS_I2C_INIT_BOARD | |
| 221 | #define CONFIG_SYS_I2C | |
| 222 | #define CONFIG_CMD_I2C | |
| 223 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ | |
| 224 | #define CONFIG_SYS_I2C_S3C24X0 | |
| 225 | #define CONFIG_I2C_MULTI_BUS | |
| 226 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 | |
| 227 | #define CONFIG_I2C_EDID | |
| 228 | ||
| 229 | /* SPI */ | |
| 230 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 231 | #define CONFIG_SPI_FLASH | |
| 232 | #define CONFIG_ENV_SPI_BASE 0x12D30000 | |
| 233 | ||
| 234 | #ifdef CONFIG_SPI_FLASH | |
| 235 | #define CONFIG_EXYNOS_SPI | |
| 236 | #define CONFIG_CMD_SF | |
| 237 | #define CONFIG_CMD_SPI | |
| 238 | #define CONFIG_SPI_FLASH_WINBOND | |
| 239 | #define CONFIG_SPI_FLASH_GIGADEVICE | |
| 240 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 241 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
| 242 | #define EXYNOS5_SPI_NUM_CONTROLLERS 5 | |
| 243 | #define CONFIG_OF_SPI | |
| 244 | #endif | |
| 245 | ||
| 246 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
| 247 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
| 248 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
| 249 | #define CONFIG_ENV_SPI_BUS 1 | |
| 250 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
| 251 | #endif | |
| 252 | ||
| 253 | /* PMIC */ | |
| 254 | #define CONFIG_POWER | |
| 255 | #define CONFIG_POWER_I2C | |
| 2469bf35 | 256 | #define CONFIG_POWER_TPS65090 |
| 76dd9b6a RS |
257 | |
| 258 | /* Ethernet Controllor Driver */ | |
| 259 | #ifdef CONFIG_CMD_NET | |
| 260 | #define CONFIG_SMC911X | |
| 261 | #define CONFIG_SMC911X_BASE 0x5000000 | |
| 262 | #define CONFIG_SMC911X_16_BIT | |
| 263 | #define CONFIG_ENV_SROM_BANK 1 | |
| 264 | #endif /*CONFIG_CMD_NET*/ | |
| 265 | ||
| 266 | /* Enable PXE Support */ | |
| 267 | #ifdef CONFIG_CMD_NET | |
| 268 | #define CONFIG_CMD_PXE | |
| 269 | #define CONFIG_MENU | |
| 270 | #endif | |
| 271 | ||
| 272 | /* Enable devicetree support */ | |
| 273 | #define CONFIG_OF_LIBFDT | |
| 274 | ||
| 275 | /* SHA hashing */ | |
| 276 | #define CONFIG_CMD_HASH | |
| 277 | #define CONFIG_HASH_VERIFY | |
| 278 | #define CONFIG_SHA1 | |
| 279 | #define CONFIG_SHA256 | |
| 280 | ||
| 281 | /* Enable Time Command */ | |
| 282 | #define CONFIG_CMD_TIME | |
| 283 | ||
| 284 | #define CONFIG_CMD_BOOTZ | |
| 285 | ||
| 9b97b727 AS |
286 | #define CONFIG_CMD_GPIO |
| 287 | ||
| 582693b2 AS |
288 | /* USB boot mode */ |
| 289 | #define CONFIG_USB_BOOTING | |
| 290 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 | |
| 291 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 | |
| 292 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 | |
| 293 | ||
| 76dd9b6a | 294 | #endif /* __CONFIG_H */ |