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0eb5717a HCE |
1 | /* |
2 | * Copyright (C) 2008 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the Favr-32 EarthLCD LCD kit. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
0eb5717a HCE |
7 | */ |
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
5d73bc7a | 11 | #include <asm/arch/hardware.h> |
0eb5717a | 12 | |
eacbfe7d AB |
13 | #define CONFIG_AT32AP |
14 | #define CONFIG_AT32AP7000 | |
15 | #define CONFIG_FAVR32_EZKIT | |
0eb5717a | 16 | |
eacbfe7d | 17 | #define CONFIG_FAVR32_EZKIT_EXT_FLASH |
0eb5717a | 18 | |
0eb5717a HCE |
19 | /* |
20 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
21 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
22 | * PLL frequency. | |
6d0f6bcf | 23 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
0eb5717a | 24 | */ |
eacbfe7d AB |
25 | #define CONFIG_PLL |
26 | #define CONFIG_SYS_POWER_MANAGER | |
6d0f6bcf JCPV |
27 | #define CONFIG_SYS_OSC0_HZ 20000000 |
28 | #define CONFIG_SYS_PLL0_DIV 1 | |
29 | #define CONFIG_SYS_PLL0_MUL 7 | |
30 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
0eb5717a HCE |
31 | /* |
32 | * Set the CPU running at: | |
6d0f6bcf | 33 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
0eb5717a | 34 | */ |
6d0f6bcf | 35 | #define CONFIG_SYS_CLKDIV_CPU 0 |
0eb5717a HCE |
36 | /* |
37 | * Set the HSB running at: | |
6d0f6bcf | 38 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
0eb5717a | 39 | */ |
6d0f6bcf | 40 | #define CONFIG_SYS_CLKDIV_HSB 1 |
0eb5717a HCE |
41 | /* |
42 | * Set the PBA running at: | |
6d0f6bcf | 43 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
0eb5717a | 44 | */ |
6d0f6bcf | 45 | #define CONFIG_SYS_CLKDIV_PBA 2 |
0eb5717a HCE |
46 | /* |
47 | * Set the PBB running at: | |
6d0f6bcf | 48 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
0eb5717a | 49 | */ |
6d0f6bcf | 50 | #define CONFIG_SYS_CLKDIV_PBB 1 |
0eb5717a | 51 | |
1f36f73f HS |
52 | /* Reserve VM regions for SDRAM and NOR flash */ |
53 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
54 | ||
0eb5717a HCE |
55 | /* |
56 | * The PLLOPT register controls the PLL like this: | |
57 | * icp = PLLOPT<2> | |
58 | * ivco = PLLOPT<1:0> | |
59 | * | |
60 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
61 | */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_PLL0_OPT 0x04 |
0eb5717a | 63 | |
f4278b71 AB |
64 | #define CONFIG_USART_BASE ATMEL_BASE_USART3 |
65 | #define CONFIG_USART_ID 3 | |
0eb5717a HCE |
66 | |
67 | /* User serviceable stuff */ | |
eacbfe7d | 68 | #define CONFIG_DOS_PARTITION |
0eb5717a | 69 | |
eacbfe7d AB |
70 | #define CONFIG_CMDLINE_TAG |
71 | #define CONFIG_SETUP_MEMORY_TAGS | |
72 | #define CONFIG_INITRD_TAG | |
0eb5717a HCE |
73 | |
74 | #define CONFIG_STACKSIZE (2048) | |
75 | ||
76 | #define CONFIG_BAUDRATE 115200 | |
77 | #define CONFIG_BOOTARGS \ | |
78 | "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" | |
79 | ||
80 | #define CONFIG_BOOTCOMMAND \ | |
81 | "fsload; bootm $(fileaddr)" | |
82 | ||
83 | /* | |
84 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
85 | * data on the serial line may interrupt the boot sequence. | |
86 | */ | |
87 | #define CONFIG_BOOTDELAY 1 | |
eacbfe7d AB |
88 | #define CONFIG_AUTOBOOT |
89 | #define CONFIG_AUTOBOOT_KEYED | |
0eb5717a | 90 | #define CONFIG_AUTOBOOT_PROMPT \ |
25da0b84 | 91 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay |
0eb5717a HCE |
92 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
93 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
94 | ||
95 | /* | |
96 | * After booting the board for the first time, new ethernet addresses | |
97 | * should be generated and assigned to the environment variables | |
98 | * "ethaddr" and "eth1addr". This is normally done during production. | |
99 | */ | |
eacbfe7d | 100 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
0eb5717a HCE |
101 | |
102 | /* | |
103 | * BOOTP options | |
104 | */ | |
105 | #define CONFIG_BOOTP_SUBNETMASK | |
106 | #define CONFIG_BOOTP_GATEWAY | |
107 | ||
108 | ||
109 | /* | |
110 | * Command line configuration. | |
111 | */ | |
112 | #include <config_cmd_default.h> | |
113 | ||
114 | #define CONFIG_CMD_ASKENV | |
115 | #define CONFIG_CMD_DHCP | |
116 | #define CONFIG_CMD_EXT2 | |
117 | #define CONFIG_CMD_FAT | |
118 | #define CONFIG_CMD_JFFS2 | |
119 | #define CONFIG_CMD_MMC | |
120 | ||
0eb5717a HCE |
121 | #undef CONFIG_CMD_FPGA |
122 | #undef CONFIG_CMD_SETGETDCR | |
74de7aef | 123 | #undef CONFIG_CMD_SOURCE |
0eb5717a HCE |
124 | #undef CONFIG_CMD_XIMG |
125 | ||
eacbfe7d AB |
126 | #define CONFIG_ATMEL_USART |
127 | #define CONFIG_MACB | |
128 | #define CONFIG_PORTMUX_PIO | |
6d0f6bcf | 129 | #define CONFIG_SYS_NR_PIOS 5 |
eacbfe7d AB |
130 | #define CONFIG_SYS_HSDRAMC |
131 | #define CONFIG_MMC | |
72fa4679 SS |
132 | #define CONFIG_GENERIC_ATMEL_MCI |
133 | #define CONFIG_GENERIC_MMC | |
0eb5717a | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
136 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
0eb5717a HCE |
137 | |
138 | #define CONFIG_NR_DRAM_BANKS 1 | |
139 | ||
140 | /* External flash on Favr-32 */ | |
141 | #if 0 | |
6d0f6bcf | 142 | #define CONFIG_SYS_FLASH_CFI 1 |
ee9536a2 | 143 | #define CONFIG_FLASH_CFI_DRIVER 1 |
0eb5717a HCE |
144 | #endif |
145 | ||
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
147 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
148 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
149 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
0eb5717a | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
8e218a99 | 152 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
0eb5717a | 153 | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
155 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
156 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
0eb5717a | 157 | |
eacbfe7d | 158 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 159 | #define CONFIG_ENV_SIZE 65536 |
6d0f6bcf | 160 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
0eb5717a | 161 | |
6d0f6bcf | 162 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
0eb5717a | 163 | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
165 | #define CONFIG_SYS_DMA_ALLOC_LEN (16384) | |
0eb5717a HCE |
166 | |
167 | /* Allow 4MB for the kernel run-time image */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
169 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
0eb5717a HCE |
170 | |
171 | /* Other configuration settings that shouldn't have to change all that often */ | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_PROMPT "U-Boot> " |
173 | #define CONFIG_SYS_CBSIZE 256 | |
174 | #define CONFIG_SYS_MAXARGS 16 | |
175 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
eacbfe7d | 176 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
177 | |
178 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
179 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
180 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
0eb5717a HCE |
181 | |
182 | #endif /* __CONFIG_H */ |