[people/ms/u-boot.git] / include / configs / galaxy5200.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2006
 * Eric Schumann, Phytec Messatechnik GmbH
 *
 * (C) Copyright 2009
 * Jon Smirl <jonsmirl@gmail.com>
 *
 * (C) Copyright 2009
 * Eric Millbrandt, DEKA Research and Development Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_BOARDINFO	 "galaxy5200"

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333	/* ... running at 33.333333MHz */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4 -> */
					/* define gps port conf. */
					/* register later on to  */
					/* enable UART function! */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_PING
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_USB
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FAT

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFE000000)		/* Boot low */
#define CONFIG_SYS_LOWBOOT 1
#endif
/* RAMBOOT will be defined automatically in memory section */

#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:256k(ubootl)," \
	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
					/* even with bootdelay=0 */
#define CONFIG_BOOT_RETRY_TIME 120	/* Reset if no command is entered  */
#define CONFIG_RESET_TO_RETRY

#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome to U-Boot;"\
	"echo"

#define CONFIG_BOOTCOMMAND     "go ff300004 0; go ff300004 2 2;" \
	"bootm ff040000 ff900000 fffc0000"
#define CONFIG_BOOTARGS        "console=ttyPSC0,115200"
#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
#define CONFIG_SYS_XLB_PIPELINING	1

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C 1		/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2		/* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_INIT_MPC5XXX	/* Reset devices on i2c bus */

/*
 * EEPROM CAT24WC32 configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* 1010100x */
#define CONFIG_SYS_I2C_FACT_ADDR	0x52	/* EEPROM CAT24WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address */
#define CONFIG_SYS_EEPROM_SIZE		4096
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Flash configuration
 */

#define CONFIG_SYS_FLASH_BASE		0xfe000000
/*
 * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
 * variable defined
 */
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_FLASH_CFI 1		/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_SECT 259	/* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max num of flash banks */
					/* (= chip selects) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * Use hardware protection. This seems required, as the BDI uses hardware
 * protection. Without this, U-Boot can't work with this sectors as its
 * protection is software only by default.
 */
#define CONFIG_SYS_FLASH_PROTECTION	1

/*
 * Environment settings
 */

#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
					/* beginning of the EEPROM */
#define CONFIG_ENV_SIZE		CONFIG_SYS_EEPROM_SIZE

#define CONFIG_ENV_OVERWRITE	1

/*
 * SDRAM configuration
 */
#define SDRAM_DDR	1
#define SDRAM_MODE	0x018D0000
#define SDRAM_EMODE	0x40090000
#define SDRAM_CONTROL	0x71500F00
#define SDRAM_CONFIG1	0x73711930
#define SDRAM_CONFIG2	0x47770000

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
					/* bootloader or debugger config */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR		0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM

/* End of used area in SPRAM */
#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE

/* Size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
						CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#	define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN (192 << 10)	/* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10)	/* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)	/* Initial Memory map for Linux */

/* Chip Select configuration for NAND flash */
#define CONFIG_SYS_CS1_START		0x20000000
#define CONFIG_SYS_CS1_SIZE		0x90000
#define CONFIG_SYS_CS1_CFG		0x00025b00

/* Chip Select configuration for Epson S1D13513 */
#define CONFIG_SYS_CS3_START		0x10000000
#define CONFIG_SYS_CS3_SIZE		0x400000
#define CONFIG_SYS_CS3_CFG		0xffff3d10

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC		1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR			0x01
#define CONFIG_NO_AUTOLOAD		1

/*
 * GPIO configuration
 *
 * GPS port configuration
 *
 * [29:31] = 01x
 * AC97 on PSC1
 * PSC1_0 -> AC97 SDATA out
 * PSC1_1 -> AC97 SDTA in
 * PSC1_2 -> AC97 SYNC out
 * PSC1_3 -> AC97 bitclock out
 * PSC1_4 -> AC97 reset out
 *
 * [28] = Reserved
 *
 * [25:27] = 110
 * SPI on PSC2
 * PSC2_0 -> MOSI
 * PSC2_1 -> MISO
 * PSC2_2 -> n/a
 * PSC2_3 -> CLK
 * PSC2_4 -> SS
 *
 * [24] = Reserved
 *
 * [20:23] = 0001
 * USB on PSC3
 * PSC3_0 -> USB_OE OE out
 * PSC3_1 -> USB_TXN Tx- out
 * PSC3_2 -> USB_TXP Tx+ out
 * PSC3_3 -> USB_TXD
 * PSC3_4 -> USB_RXP Rx+ in
 * PSC3_5 -> USB_RXN Rx- in
 * PSC3_6 -> USB_PWR PortPower out
 * PSC3_7 -> USB_SPEED speed out
 * PSC3_8 -> USB_SUSPEND suspend
 * PSC3_9 -> USB_OVRCURNT overcurrent in
 *
 * [18:19] = 10
 * Two UARTs
 *
 * [17] = 0
 * USB differential mode
 *
 * [16] = 1
 * PCI disabled
 *
 * [12:15] = 0101
 * Ethernet 100Mbit with MD
 * ETH_0 -> ETH Txen
 * ETH_1 -> ETH TxD0
 * ETH_2 -> ETH TxD1
 * ETH_3 -> ETH TxD2
 * ETH_4 -> ETH TxD3
 * ETH_5 -> ETH Txerr
 * ETH_6 -> ETH MDC
 * ETH_7 -> ETH MDIO
 * ETH_8 -> ETH RxDv
 * ETH_9 -> ETH RxCLK
 * ETH_10 -> ETH Collision
 * ETH_11 -> ETH TxD
 * ETH_12 -> ETH RxD0
 * ETH_13 -> ETH RxD1
 * ETH_14 -> ETH RxD2
 * ETH_15 -> ETH RxD3
 * ETH_16 -> ETH Rxerr
 * ETH_17 -> ETH CRS
 *
 * [9:11] = 111
 * SPI on PSC6
 * PSC6_0 -> MISO
 * PSC6_1 -> SS#
 * PSC6_2 -> MOSI
 * PSC6_3 -> CLK
 *
 * [8] = 0
 * IrDA/USB 48MHz clock generated internally
 *
 * [6:7] = 01
 * ATA chip selects on csb_4/5
 * CSB_4 -> ATA_CS0 out
 * CSB_5 -> ATA_CS1 out
 *
 * [5] = 1
 * PSC3_4 is used as CS6
 *
 * [4] = 1
 * PSC3_5 is used as CS7
 *
 * [2:3] = 00
 * No Alternatives
 *
 * [1] = 0
 * gpio_wkup_7 is GPIO
 *
 * [0] = 0
 * gpio_wkup_6 is GPIO
 *
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x0d75a162

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_PROMPT "uboot> "		/* Monitor Command Prompt */

#define CONFIG_CMDLINE_EDITING 1		/* add command line history */

#define CONFIG_SYS_CACHELINE_SIZE 32		/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 5		/* log base 2 of the above value */
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024			/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 512			/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 32			/* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000	/* 1 ... 15 MB in DRAM */

#define CONFIG_SYS_LOAD_ADDR 0x400000		/* default load address */
#define CONFIG_SYS_HZ 1000			/* decrementer freq: 1 ms ticks */

#define CONFIG_DISPLAY_BOARDINFO 1

#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

#define CONFIG_CRC32_VERIFY  1

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
				 CONFIG_BOOTP_DNS | \
				 CONFIG_BOOTP_DNS2 | \
				 CONFIG_BOOTP_SEND_HOSTNAME )

#define CONFIG_VERSION_VARIABLE 1

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

/* no burst access on the LPB */
#define CONFIG_SYS_CS_BURST		0x00000000
/* one deadcycle for the 33MHz statemachine */
#define CONFIG_SYS_CS_DEADCYCLE		0x33333331

#define CONFIG_SYS_BOOTCS_CFG		0x0002d900
#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * USB settings
 */
#define CONFIG_USB_CLOCK		0x0001bbbb
/* USB is on PSC3 */
#define CONFIG_PSC3_USB
#define CONFIG_USB_CONFIG		0x00000100
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/*
 * IDE/ATA stuff Supports IDE harddisk
 */
#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
#undef	CONFIG_IDE_LED		/* LED for ide not supported */

#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1	/* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 2	/* max. 2 drives per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE		4
#define CONFIG_ATAPI			1

/* we enable IDE and FAT support, so we also need partition support */
#define CONFIG_DOS_PARTITION 1

/*
 * Open Firmware flat tree
 */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1

#define OF_CPU				"PowerPC,5200@0"
#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
#define OF_SOC				"soc5200@f0000000"
#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2600"

#endif /* __CONFIG_H */
Commit	Line	Data
5b53b29b EM	1	/*
	2	* (C) Copyright 2003-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Eric Schumann, Phytec Messatechnik GmbH
	7	*
	8	* (C) Copyright 2009
	9	* Jon Smirl <jonsmirl@gmail.com>
	10	*
	11	* (C) Copyright 2009
	12	* Eric Millbrandt, DEKA Research and Development Corporation
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	#define CONFIG_BOARDINFO "galaxy5200"
	37
	38	/*
	39	* High Level Configuration Options
	40	* (easy to change)
	41	*/
	42	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	43	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	44	#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
	45	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	46	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	47
	48	/*
	49	* Serial console configuration
	50	*/
	51	#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
	52	/* define gps port conf. */
	53	/* register later on to */
	54	/* enable UART function! */
	55	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	56	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	57
	58	/*
	59	* Command line configuration.
	60	*/
	61	#include <config_cmd_default.h>
	62
	63	#define CONFIG_CMD_DATE
	64	#define CONFIG_CMD_DHCP
65	#define CONFIG_CMD_EEPROM
66	#define CONFIG_CMD_I2C
67	#define CONFIG_CMD_JFFS2
68	#define CONFIG_CMD_MII
69	#define CONFIG_CMD_NFS
70	#define CONFIG_CMD_SNTP
71	#define CONFIG_CMD_PING
72	#define CONFIG_CMD_ASKENV
73	#define CONFIG_CMD_USB
74	#define CONFIG_CMD_CACHE
75	#define CONFIG_CMD_FAT
76
77	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
78
79	#if (TEXT_BASE == 0xFE000000) /* Boot low */
80	#define CONFIG_SYS_LOWBOOT 1
81	#endif
82	/* RAMBOOT will be defined automatically in memory section */
83
0d042037 EM	84	#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
0d042037 EM	85	#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
5b53b29b EM	86	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
	87
	88	/*
	89	* Autobooting
	90	*/
353462f6	91	#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
5b53b29b EM	92	#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
5b53b29b EM	93	/* even with bootdelay=0 */
353462f6 EM	94	#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
353462f6 EM	95	#define CONFIG_RESET_TO_RETRY
5b53b29b EM	96
5b53b29b EM	97	#define CONFIG_PREBOOT "echo;" \
0d042037	98	"echo Welcome to U-Boot;"\
5b53b29b EM	99	"echo"
5b53b29b EM	100
353462f6 EM	101	#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
	102	"bootm ff040000 ff900000 fffc0000"
	103	#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
	104	#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
	105
5b53b29b EM	106	/*
	107	* IPB Bus clocking configuration.
	108	*/
	109	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	110	#define CONFIG_SYS_XLB_PIPELINING 1
	111
	112	/*
	113	* I2C configuration
	114	*/
	115	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	116	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	117	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	118	#define CONFIG_SYS_I2C_SLAVE 0x7F
5da71efa	119	#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
5b53b29b EM	120
	121	/*
	122	* EEPROM CAT24WC32 configuration
	123	*/
	124	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
	125	#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
	126	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	127	#define CONFIG_SYS_EEPROM_SIZE 4096
	128	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	129	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
	130
	131	/*
	132	* RTC configuration
	133	*/
	134	#define RTC
	135	#define CONFIG_RTC_DS3231 1
	136	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	137
	138	/*
	139	* Flash configuration
	140	*/
	141
	142	#define CONFIG_SYS_FLASH_BASE 0xfe000000
	143	/*
a47a12be	144	* The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
5b53b29b EM	145	* variable defined
	146	*/
	147	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	148	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	149
	150	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
	151	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	152	#define CONFIG_SYS_FLASH_EMPTY_INFO
	153	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
	154	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	155	/* (= chip selects) */
	156	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	157
	158	/*
	159	* Use hardware protection. This seems required, as the BDI uses hardware
	160	* protection. Without this, U-Boot can't work with this sectors as its
	161	* protection is software only by default.
	162	*/
	163	#define CONFIG_SYS_FLASH_PROTECTION 1
	164
	165	/*
	166	* Environment settings
	167	*/
	168
	169	#define CONFIG_ENV_IS_IN_EEPROM 1
	170	#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
	171	/* beginning of the EEPROM */
	172	#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
	173
	174	#define CONFIG_ENV_OVERWRITE 1
	175
	176	/*
	177	* SDRAM configuration
	178	*/
	179	#define SDRAM_DDR 1
	180	#define SDRAM_MODE 0x018D0000
	181	#define SDRAM_EMODE 0x40090000
	182	#define SDRAM_CONTROL 0x71500F00
	183	#define SDRAM_CONFIG1 0x73711930
	184	#define SDRAM_CONFIG2 0x47770000
	185
	186	/*
	187	* Memory map
	188	*/
	189	#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
	190	/* bootloader or debugger config */
	191	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	192	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	193
	194	/* Use SRAM until RAM will be available */
	195	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
	196
	197	/* End of used area in SPRAM */
	198	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
	199
	200	/* Size in bytes reserved for initial data */
	201	#define CONFIG_SYS_GBL_DATA_SIZE 128
	202
	203	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
	204	CONFIG_SYS_GBL_DATA_SIZE)
	205	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	206
	207	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	208	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209	# define CONFIG_SYS_RAMBOOT 1
210	#endif
211
212	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
213	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
214	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
215
216	/* Chip Select configuration for NAND flash */
217	#define CONFIG_SYS_CS1_START 0x20000000
218	#define CONFIG_SYS_CS1_SIZE 0x90000
45def0ab	219	#define CONFIG_SYS_CS1_CFG 0x00025b00
5b53b29b	220
795d246c EM	221	/* Chip Select configuration for Epson S1D13513 */
	222	#define CONFIG_SYS_CS3_START 0x10000000
	223	#define CONFIG_SYS_CS3_SIZE 0x400000
	224	#define CONFIG_SYS_CS3_CFG 0xffff3d10
	225
5b53b29b EM	226	/*
	227	* Ethernet configuration
	228	*/
	229	#define CONFIG_MPC5xxx_FEC 1
	230	#define CONFIG_MPC5xxx_FEC_MII100
	231	#define CONFIG_PHY_ADDR 0x01
	232	#define CONFIG_NO_AUTOLOAD 1
	233
	234	/*
	235	* GPIO configuration
	236	*
	237	* GPS port configuration
	238	*
	239	* [29:31] = 01x
	240	* AC97 on PSC1
	241	* PSC1_0 -> AC97 SDATA out
	242	* PSC1_1 -> AC97 SDTA in
	243	* PSC1_2 -> AC97 SYNC out
	244	* PSC1_3 -> AC97 bitclock out
	245	* PSC1_4 -> AC97 reset out
	246	*
	247	* [28] = Reserved
	248	*
	249	* [25:27] = 110
	250	* SPI on PSC2
	251	* PSC2_0 -> MOSI
	252	* PSC2_1 -> MISO
	253	* PSC2_2 -> n/a
	254	* PSC2_3 -> CLK
	255	* PSC2_4 -> SS
	256	*
	257	* [24] = Reserved
	258	*
	259	* [20:23] = 0001
	260	* USB on PSC3
	261	* PSC3_0 -> USB_OE OE out
	262	* PSC3_1 -> USB_TXN Tx- out
	263	* PSC3_2 -> USB_TXP Tx+ out
	264	* PSC3_3 -> USB_TXD
	265	* PSC3_4 -> USB_RXP Rx+ in
	266	* PSC3_5 -> USB_RXN Rx- in
	267	* PSC3_6 -> USB_PWR PortPower out
	268	* PSC3_7 -> USB_SPEED speed out
	269	* PSC3_8 -> USB_SUSPEND suspend
	270	* PSC3_9 -> USB_OVRCURNT overcurrent in
	271	*
	272	* [18:19] = 10
	273	* Two UARTs
	274	*
	275	* [17] = 0
	276	* USB differential mode
	277	*
	278	* [16] = 1
	279	* PCI disabled
	280	*
	281	* [12:15] = 0101
	282	* Ethernet 100Mbit with MD
	283	* ETH_0 -> ETH Txen
	284	* ETH_1 -> ETH TxD0
	285	* ETH_2 -> ETH TxD1
	286	* ETH_3 -> ETH TxD2
	287	* ETH_4 -> ETH TxD3
	288	* ETH_5 -> ETH Txerr
	289	* ETH_6 -> ETH MDC
290	* ETH_7 -> ETH MDIO
291	* ETH_8 -> ETH RxDv
292	* ETH_9 -> ETH RxCLK
293	* ETH_10 -> ETH Collision
294	* ETH_11 -> ETH TxD
295	* ETH_12 -> ETH RxD0
296	* ETH_13 -> ETH RxD1
297	* ETH_14 -> ETH RxD2
298	* ETH_15 -> ETH RxD3
299	* ETH_16 -> ETH Rxerr
300	* ETH_17 -> ETH CRS
301	*
302	* [9:11] = 111
303	* SPI on PSC6
304	* PSC6_0 -> MISO
305	* PSC6_1 -> SS#
306	* PSC6_2 -> MOSI
307	* PSC6_3 -> CLK
308	*
309	* [8] = 0
310	* IrDA/USB 48MHz clock generated internally
311	*
312	* [6:7] = 01
313	* ATA chip selects on csb_4/5
314	* CSB_4 -> ATA_CS0 out
315	* CSB_5 -> ATA_CS1 out
316	*
317	* [5] = 1
318	* PSC3_4 is used as CS6
319	*
320	* [4] = 1
321	* PSC3_5 is used as CS7
322	*
323	* [2:3] = 00
324	* No Alternatives
325	*
326	* [1] = 0
327	* gpio_wkup_7 is GPIO
328	*
329	* [0] = 0
330	* gpio_wkup_6 is GPIO
331	*
332	*/
333	#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
334
335	/*
336	* Miscellaneous configurable options
337	*/
338	#define CONFIG_SYS_LONGHELP /* undef to save memory */
339	#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
340
341	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
342
343	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
344	#if defined(CONFIG_CMD_KGDB)
345	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
346	#endif
347
348	#if defined(CONFIG_CMD_KGDB)
349	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
350	#else
351	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
352	#endif
353	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
354	/* Print Buffer Size */
355	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
356	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
357
358	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
359	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
360
361	#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
362	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
363
364	#define CONFIG_DISPLAY_BOARDINFO 1
365
366	#define CONFIG_SYS_HUSH_PARSER 1
367	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
368
369	#define CONFIG_CRC32_VERIFY 1
370
371	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| \
372	CONFIG_BOOTP_DNS \| \
373	CONFIG_BOOTP_DNS2 \| \
374	CONFIG_BOOTP_SEND_HOSTNAME )
375
71ce9bd7 EM	376	#define CONFIG_VERSION_VARIABLE 1
71ce9bd7 EM	377
5b53b29b EM	378	/*
	379	* Various low-level settings
	380	*/
	381	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	382	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	383
	384	/* no burst access on the LPB */
	385	#define CONFIG_SYS_CS_BURST 0x00000000
	386	/* one deadcycle for the 33MHz statemachine */
	387	#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
	388
	389	#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
	390	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	391	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	392
0d042037	393	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
5b53b29b EM	394
	395	/*
	396	* USB settings
	397	*/
	398	#define CONFIG_USB_CLOCK 0x0001bbbb
	399	/* USB is on PSC3 */
	400	#define CONFIG_PSC3_USB
	401	#define CONFIG_USB_CONFIG 0x00000100
	402	#define CONFIG_USB_OHCI
	403	#define CONFIG_USB_STORAGE
	404
	405	/*
	406	* IDE/ATA stuff Supports IDE harddisk
	407	*/
	408	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	409	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	410	#undef CONFIG_IDE_LED /* LED for ide not supported */
	411
	412	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	413	#define CONFIG_IDE_PREINIT
	414	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	415	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
	416	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	417	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	418	/* Offset for data I/O */
	419	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	420	/* Offset for normal register accesses */
	421	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
	422	/* Offset for alternate registers */
	423	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
	424	/* Interval between registers */
	425	#define CONFIG_SYS_ATA_STRIDE 4
	426	#define CONFIG_ATAPI 1
	427
	428	/* we enable IDE and FAT support, so we also need partition support */
	429	#define CONFIG_DOS_PARTITION 1
	430
	431	/*
	432	* Open Firmware flat tree
	433	*/
	434	#define CONFIG_OF_LIBFDT 1
	435	#define CONFIG_OF_BOARD_SETUP 1
	436
	437	#define OF_CPU "PowerPC,5200@0"
	438	#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
	439	#define OF_SOC "soc5200@f0000000"
	440	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
	441
	442	#endif /* __CONFIG_H */