]>
Commit | Line | Data |
---|---|---|
5b53b29b EM |
1 | /* |
2 | * (C) Copyright 2003-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Eric Schumann, Phytec Messatechnik GmbH | |
7 | * | |
8 | * (C) Copyright 2009 | |
9 | * Jon Smirl <jonsmirl@gmail.com> | |
10 | * | |
11 | * (C) Copyright 2009 | |
12 | * Eric Millbrandt, DEKA Research and Development Corporation | |
13 | * | |
14 | * See file CREDITS for list of people who contributed to this | |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | #define CONFIG_BOARDINFO "galaxy5200" | |
37 | ||
38 | /* | |
39 | * High Level Configuration Options | |
40 | * (easy to change) | |
41 | */ | |
42 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
43 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
44 | #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ | |
5b53b29b | 45 | |
2ae18241 WD |
46 | /* |
47 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
48 | * 0xFFF00000 boot high (standard configuration) | |
49 | * 0xFE000000 boot low | |
50 | * 0x00100000 boot from RAM (for testing only) does not work | |
51 | */ | |
52 | #ifdef CONFIG_galaxy5200_LOWBOOT | |
53 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
54 | #endif | |
55 | ||
56 | #ifndef CONFIG_SYS_TEXT_BASE | |
57 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ | |
58 | #endif | |
59 | ||
5b53b29b EM |
60 | /* |
61 | * Serial console configuration | |
62 | */ | |
63 | #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */ | |
64 | /* define gps port conf. */ | |
65 | /* register later on to */ | |
66 | /* enable UART function! */ | |
67 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
68 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
69 | ||
70 | /* | |
71 | * Command line configuration. | |
72 | */ | |
73 | #include <config_cmd_default.h> | |
74 | ||
75 | #define CONFIG_CMD_DATE | |
76 | #define CONFIG_CMD_DHCP | |
77 | #define CONFIG_CMD_EEPROM | |
78 | #define CONFIG_CMD_I2C | |
79 | #define CONFIG_CMD_JFFS2 | |
80 | #define CONFIG_CMD_MII | |
81 | #define CONFIG_CMD_NFS | |
82 | #define CONFIG_CMD_SNTP | |
83 | #define CONFIG_CMD_PING | |
84 | #define CONFIG_CMD_ASKENV | |
85 | #define CONFIG_CMD_USB | |
86 | #define CONFIG_CMD_CACHE | |
87 | #define CONFIG_CMD_FAT | |
88 | ||
89 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
90 | ||
14d0a02a | 91 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ |
5b53b29b EM |
92 | #define CONFIG_SYS_LOWBOOT 1 |
93 | #endif | |
94 | /* RAMBOOT will be defined automatically in memory section */ | |
95 | ||
0d042037 EM |
96 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0" |
97 | #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ | |
5b53b29b EM |
98 | "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" |
99 | ||
100 | /* | |
101 | * Autobooting | |
102 | */ | |
353462f6 | 103 | #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ |
5b53b29b EM |
104 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ |
105 | /* even with bootdelay=0 */ | |
353462f6 EM |
106 | #define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */ |
107 | #define CONFIG_RESET_TO_RETRY | |
5b53b29b EM |
108 | |
109 | #define CONFIG_PREBOOT "echo;" \ | |
0d042037 | 110 | "echo Welcome to U-Boot;"\ |
5b53b29b EM |
111 | "echo" |
112 | ||
353462f6 EM |
113 | #define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \ |
114 | "bootm ff040000 ff900000 fffc0000" | |
115 | #define CONFIG_BOOTARGS "console=ttyPSC0,115200" | |
116 | #define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0" | |
117 | ||
5b53b29b EM |
118 | /* |
119 | * IPB Bus clocking configuration. | |
120 | */ | |
121 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ | |
122 | #define CONFIG_SYS_XLB_PIPELINING 1 | |
123 | ||
124 | /* | |
125 | * I2C configuration | |
126 | */ | |
127 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
128 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ | |
129 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
130 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
5da71efa | 131 | #define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */ |
5b53b29b EM |
132 | |
133 | /* | |
134 | * EEPROM CAT24WC32 configuration | |
135 | */ | |
136 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ | |
137 | #define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ | |
138 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
139 | #define CONFIG_SYS_EEPROM_SIZE 4096 | |
140 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
141 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 | |
142 | ||
143 | /* | |
144 | * RTC configuration | |
145 | */ | |
146 | #define RTC | |
147 | #define CONFIG_RTC_DS3231 1 | |
148 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
149 | ||
150 | /* | |
151 | * Flash configuration | |
152 | */ | |
153 | ||
154 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 | |
155 | /* | |
a47a12be | 156 | * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this |
5b53b29b EM |
157 | * variable defined |
158 | */ | |
159 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
160 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
161 | ||
162 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
163 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
164 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
165 | #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */ | |
166 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
167 | /* (= chip selects) */ | |
168 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
169 | ||
170 | /* | |
171 | * Use hardware protection. This seems required, as the BDI uses hardware | |
172 | * protection. Without this, U-Boot can't work with this sectors as its | |
173 | * protection is software only by default. | |
174 | */ | |
175 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
176 | ||
177 | /* | |
178 | * Environment settings | |
179 | */ | |
180 | ||
181 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
182 | #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ | |
183 | /* beginning of the EEPROM */ | |
184 | #define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE | |
185 | ||
186 | #define CONFIG_ENV_OVERWRITE 1 | |
187 | ||
188 | /* | |
189 | * SDRAM configuration | |
190 | */ | |
191 | #define SDRAM_DDR 1 | |
192 | #define SDRAM_MODE 0x018D0000 | |
193 | #define SDRAM_EMODE 0x40090000 | |
194 | #define SDRAM_CONTROL 0x71500F00 | |
195 | #define SDRAM_CONFIG1 0x73711930 | |
196 | #define SDRAM_CONFIG2 0x47770000 | |
197 | ||
198 | /* | |
199 | * Memory map | |
200 | */ | |
201 | #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ | |
202 | /* bootloader or debugger config */ | |
203 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
204 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
205 | ||
206 | /* Use SRAM until RAM will be available */ | |
207 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
208 | ||
209 | /* End of used area in SPRAM */ | |
553f0982 | 210 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
5b53b29b | 211 | |
553f0982 | 212 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 213 | GENERATED_GBL_DATA_SIZE) |
5b53b29b EM |
214 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
215 | ||
14d0a02a | 216 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
5b53b29b EM |
217 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
218 | # define CONFIG_SYS_RAMBOOT 1 | |
219 | #endif | |
220 | ||
221 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
222 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
223 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
224 | ||
225 | /* Chip Select configuration for NAND flash */ | |
226 | #define CONFIG_SYS_CS1_START 0x20000000 | |
227 | #define CONFIG_SYS_CS1_SIZE 0x90000 | |
45def0ab | 228 | #define CONFIG_SYS_CS1_CFG 0x00025b00 |
5b53b29b | 229 | |
795d246c EM |
230 | /* Chip Select configuration for Epson S1D13513 */ |
231 | #define CONFIG_SYS_CS3_START 0x10000000 | |
232 | #define CONFIG_SYS_CS3_SIZE 0x400000 | |
233 | #define CONFIG_SYS_CS3_CFG 0xffff3d10 | |
234 | ||
5b53b29b EM |
235 | /* |
236 | * Ethernet configuration | |
237 | */ | |
238 | #define CONFIG_MPC5xxx_FEC 1 | |
239 | #define CONFIG_MPC5xxx_FEC_MII100 | |
240 | #define CONFIG_PHY_ADDR 0x01 | |
241 | #define CONFIG_NO_AUTOLOAD 1 | |
242 | ||
243 | /* | |
244 | * GPIO configuration | |
245 | * | |
246 | * GPS port configuration | |
247 | * | |
248 | * [29:31] = 01x | |
249 | * AC97 on PSC1 | |
250 | * PSC1_0 -> AC97 SDATA out | |
251 | * PSC1_1 -> AC97 SDTA in | |
252 | * PSC1_2 -> AC97 SYNC out | |
253 | * PSC1_3 -> AC97 bitclock out | |
254 | * PSC1_4 -> AC97 reset out | |
255 | * | |
256 | * [28] = Reserved | |
257 | * | |
258 | * [25:27] = 110 | |
259 | * SPI on PSC2 | |
260 | * PSC2_0 -> MOSI | |
261 | * PSC2_1 -> MISO | |
262 | * PSC2_2 -> n/a | |
263 | * PSC2_3 -> CLK | |
264 | * PSC2_4 -> SS | |
265 | * | |
266 | * [24] = Reserved | |
267 | * | |
268 | * [20:23] = 0001 | |
269 | * USB on PSC3 | |
270 | * PSC3_0 -> USB_OE OE out | |
271 | * PSC3_1 -> USB_TXN Tx- out | |
272 | * PSC3_2 -> USB_TXP Tx+ out | |
273 | * PSC3_3 -> USB_TXD | |
274 | * PSC3_4 -> USB_RXP Rx+ in | |
275 | * PSC3_5 -> USB_RXN Rx- in | |
276 | * PSC3_6 -> USB_PWR PortPower out | |
277 | * PSC3_7 -> USB_SPEED speed out | |
278 | * PSC3_8 -> USB_SUSPEND suspend | |
279 | * PSC3_9 -> USB_OVRCURNT overcurrent in | |
280 | * | |
281 | * [18:19] = 10 | |
282 | * Two UARTs | |
283 | * | |
284 | * [17] = 0 | |
285 | * USB differential mode | |
286 | * | |
287 | * [16] = 1 | |
288 | * PCI disabled | |
289 | * | |
290 | * [12:15] = 0101 | |
291 | * Ethernet 100Mbit with MD | |
292 | * ETH_0 -> ETH Txen | |
293 | * ETH_1 -> ETH TxD0 | |
294 | * ETH_2 -> ETH TxD1 | |
295 | * ETH_3 -> ETH TxD2 | |
296 | * ETH_4 -> ETH TxD3 | |
297 | * ETH_5 -> ETH Txerr | |
298 | * ETH_6 -> ETH MDC | |
299 | * ETH_7 -> ETH MDIO | |
300 | * ETH_8 -> ETH RxDv | |
301 | * ETH_9 -> ETH RxCLK | |
302 | * ETH_10 -> ETH Collision | |
303 | * ETH_11 -> ETH TxD | |
304 | * ETH_12 -> ETH RxD0 | |
305 | * ETH_13 -> ETH RxD1 | |
306 | * ETH_14 -> ETH RxD2 | |
307 | * ETH_15 -> ETH RxD3 | |
308 | * ETH_16 -> ETH Rxerr | |
309 | * ETH_17 -> ETH CRS | |
310 | * | |
311 | * [9:11] = 111 | |
312 | * SPI on PSC6 | |
313 | * PSC6_0 -> MISO | |
314 | * PSC6_1 -> SS# | |
315 | * PSC6_2 -> MOSI | |
316 | * PSC6_3 -> CLK | |
317 | * | |
318 | * [8] = 0 | |
319 | * IrDA/USB 48MHz clock generated internally | |
320 | * | |
321 | * [6:7] = 01 | |
322 | * ATA chip selects on csb_4/5 | |
323 | * CSB_4 -> ATA_CS0 out | |
324 | * CSB_5 -> ATA_CS1 out | |
325 | * | |
326 | * [5] = 1 | |
327 | * PSC3_4 is used as CS6 | |
328 | * | |
329 | * [4] = 1 | |
330 | * PSC3_5 is used as CS7 | |
331 | * | |
332 | * [2:3] = 00 | |
333 | * No Alternatives | |
334 | * | |
335 | * [1] = 0 | |
336 | * gpio_wkup_7 is GPIO | |
337 | * | |
338 | * [0] = 0 | |
339 | * gpio_wkup_6 is GPIO | |
340 | * | |
341 | */ | |
342 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162 | |
343 | ||
344 | /* | |
345 | * Miscellaneous configurable options | |
346 | */ | |
347 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
348 | #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ | |
349 | ||
350 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
351 | ||
352 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ | |
353 | #if defined(CONFIG_CMD_KGDB) | |
354 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
355 | #endif | |
356 | ||
357 | #if defined(CONFIG_CMD_KGDB) | |
358 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
359 | #else | |
360 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
361 | #endif | |
362 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
363 | /* Print Buffer Size */ | |
364 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
365 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
366 | ||
367 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
368 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
369 | ||
370 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ | |
371 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
372 | ||
373 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
374 | ||
375 | #define CONFIG_SYS_HUSH_PARSER 1 | |
5b53b29b EM |
376 | |
377 | #define CONFIG_CRC32_VERIFY 1 | |
378 | ||
379 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ | |
380 | CONFIG_BOOTP_DNS | \ | |
381 | CONFIG_BOOTP_DNS2 | \ | |
382 | CONFIG_BOOTP_SEND_HOSTNAME ) | |
383 | ||
71ce9bd7 EM |
384 | #define CONFIG_VERSION_VARIABLE 1 |
385 | ||
5b53b29b EM |
386 | /* |
387 | * Various low-level settings | |
388 | */ | |
389 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI | |
390 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
391 | ||
392 | /* no burst access on the LPB */ | |
393 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
394 | /* one deadcycle for the 33MHz statemachine */ | |
395 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333331 | |
396 | ||
397 | #define CONFIG_SYS_BOOTCS_CFG 0x0002d900 | |
398 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
399 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
400 | ||
0d042037 | 401 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
5b53b29b EM |
402 | |
403 | /* | |
404 | * USB settings | |
405 | */ | |
406 | #define CONFIG_USB_CLOCK 0x0001bbbb | |
407 | /* USB is on PSC3 */ | |
408 | #define CONFIG_PSC3_USB | |
409 | #define CONFIG_USB_CONFIG 0x00000100 | |
410 | #define CONFIG_USB_OHCI | |
411 | #define CONFIG_USB_STORAGE | |
412 | ||
413 | /* | |
414 | * IDE/ATA stuff Supports IDE harddisk | |
415 | */ | |
416 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
417 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
418 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
419 | ||
420 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
421 | #define CONFIG_IDE_PREINIT | |
422 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
423 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
424 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
425 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
426 | /* Offset for data I/O */ | |
427 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
428 | /* Offset for normal register accesses */ | |
429 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
430 | /* Offset for alternate registers */ | |
431 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
432 | /* Interval between registers */ | |
433 | #define CONFIG_SYS_ATA_STRIDE 4 | |
434 | #define CONFIG_ATAPI 1 | |
435 | ||
436 | /* we enable IDE and FAT support, so we also need partition support */ | |
437 | #define CONFIG_DOS_PARTITION 1 | |
438 | ||
439 | /* | |
440 | * Open Firmware flat tree | |
441 | */ | |
442 | #define CONFIG_OF_LIBFDT 1 | |
443 | #define CONFIG_OF_BOARD_SETUP 1 | |
444 | ||
445 | #define OF_CPU "PowerPC,5200@0" | |
446 | #define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN | |
447 | #define OF_SOC "soc5200@f0000000" | |
448 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600" | |
449 | ||
450 | #endif /* __CONFIG_H */ |