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89b8619a DE |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * Based on include/configs/yosemite.h | |
6 | * (C) Copyright 2005-2007 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
89b8619a DE |
10 | */ |
11 | ||
12 | /* | |
13 | * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module | |
14 | */ | |
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * High Level Configuration Options | |
20 | */ | |
21 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ | |
22 | #define CONFIG_HOSTNAME gdppc440etx | |
23 | #define CONFIG_440 1 /* ... PPC440 family */ | |
89b8619a DE |
24 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
25 | ||
2ae18241 WD |
26 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
27 | ||
89b8619a DE |
28 | /* |
29 | * Include common defines/options for all AMCC eval boards | |
30 | */ | |
31 | #include "amcc-common.h" | |
32 | ||
33 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ | |
34 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
35 | ||
996d88d8 | 36 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
996d88d8 | 37 | |
89b8619a DE |
38 | /* |
39 | * Base addresses -- Note these are effective addresses where the | |
40 | * actual resources get mapped (not physical addresses) | |
41 | */ | |
42 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
43 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ | |
44 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
45 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
46 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
47 | ||
48 | /*Don't change either of these*/ | |
89b8619a DE |
49 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ |
50 | /*Don't change either of these*/ | |
51 | ||
52 | #define CONFIG_SYS_USB_DEVICE 0x50000000 | |
53 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
54 | ||
55 | /* | |
56 | * Initial RAM & stack pointer (placed in SDRAM) | |
57 | */ | |
58 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ | |
59 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 60 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
553f0982 | 61 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
25ddd1fb | 62 | - GENERATED_GBL_DATA_SIZE) |
89b8619a DE |
63 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
64 | ||
65 | /* | |
66 | * Serial Port | |
67 | */ | |
550650dd SR |
68 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
69 | #define CONFIG_SYS_NS16550 | |
70 | #define CONFIG_SYS_NS16550_SERIAL | |
71 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
72 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
89b8619a | 73 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
89b8619a DE |
74 | |
75 | /* | |
76 | * Environment | |
77 | * Define here the location of the environment variables (FLASH or EEPROM). | |
78 | * Note: DENX encourages to use redundant environment in FLASH. | |
79 | */ | |
80 | #define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ | |
81 | ||
82 | /* | |
83 | * FLASH related | |
84 | */ | |
85 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ | |
86 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
87 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ | |
88 | ||
89 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
90 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ | |
91 | ||
92 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ | |
93 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ | |
94 | ||
95 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ | |
96 | ||
97 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
98 | ||
99 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
100 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ | |
101 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) | |
102 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ | |
103 | ||
104 | /* Address and size of Redundant Environment Sector */ | |
105 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
106 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
107 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
108 | ||
109 | /* | |
110 | * DDR SDRAM | |
111 | */ | |
112 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ | |
113 | #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ | |
114 | #define CONFIG_SYS_SDRAM_BANKS (2) | |
115 | ||
116 | #define CONFIG_SDRAM_BANK0 | |
117 | #define CONFIG_SDRAM_BANK1 | |
118 | ||
119 | #define CONFIG_SYS_SDRAM0_TR0 0x410a4012 | |
120 | #define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 | |
121 | #define CONFIG_SYS_SDRAM0_RTR 0x04080000 | |
122 | #define CONFIG_SYS_SDRAM0_CFG0 0x80000000 | |
123 | ||
124 | #undef CONFIG_SDRAM_ECC | |
125 | ||
126 | /* | |
127 | * I2C | |
128 | */ | |
880540de | 129 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
89b8619a DE |
130 | |
131 | /* | |
132 | * Default environment variables | |
133 | */ | |
134 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
135 | CONFIG_AMCC_DEF_ENV \ | |
136 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
137 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
138 | "kernel_addr=fc000000\0" \ | |
139 | "ramdisk_addr=fc180000\0" \ | |
140 | "" | |
141 | ||
142 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
143 | #define CONFIG_PHY_ADDR 1 | |
144 | #define CONFIG_PHY1_ADDR 3 | |
145 | ||
146 | #ifdef DEBUG | |
147 | #define CONFIG_PANIC_HANG | |
148 | #endif | |
149 | ||
150 | /* | |
151 | * Commands additional to the ones defined in amcc-common.h | |
152 | */ | |
153 | #define CONFIG_CMD_PCI | |
154 | #undef CONFIG_CMD_EEPROM | |
155 | ||
156 | /* | |
157 | * PCI stuff | |
158 | */ | |
159 | ||
160 | /* General PCI */ | |
161 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 162 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
89b8619a DE |
163 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
164 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ | |
165 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ | |
166 | CONFIG_SYS_PCI_MEMBASE*/ | |
167 | ||
168 | /* Board-specific PCI */ | |
169 | #define CONFIG_SYS_PCI_TARGET_INIT | |
170 | #define CONFIG_SYS_PCI_MASTER_INIT | |
171 | ||
172 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
173 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ | |
174 | ||
175 | /* | |
176 | * External Bus Controller (EBC) Setup | |
177 | */ | |
178 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE | |
179 | ||
180 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
181 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 | |
182 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) | |
183 | ||
184 | #endif /* __CONFIG_H */ |