[thirdparty/u-boot.git] / include / configs / ge_bx50v3.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2015 Timesys Corporation
 * Copyright (C) 2015 General Electric Company
 * Copyright (C) 2014 Advantech
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the GE MX6Q Bx50v3 boards.
 */

#ifndef __GE_BX50V3_CONFIG_H
#define __GE_BX50V3_CONFIG_H

#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>

#define BX50V3_BOOTARGS_EXTRA
#if defined(CONFIG_TARGET_GE_B450V3)
#define CONFIG_BOARD_NAME	"General Electric B450v3"
#elif defined(CONFIG_TARGET_GE_B650V3)
#define CONFIG_BOARD_NAME	"General Electric B650v3"
#elif defined(CONFIG_TARGET_GE_B850V3)
#define CONFIG_BOARD_NAME	"General Electric B850v3"
#undef BX50V3_BOOTARGS_EXTRA
#define BX50V3_BOOTARGS_EXTRA	"video=DP-1:1024x768@60 " \
				"video=HDMI-A-1:1024x768@60 "
#else
#define CONFIG_BOARD_NAME	"General Electric BA16 Generic"
#endif

#define CONFIG_MXC_UART_BASE	UART3_BASE
#define CONSOLE_DEV	"ttymxc2"

#define CONFIG_SUPPORT_EMMC_BOOT


#include "mx6_common.h"
#include <linux/sizes.h>

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)

#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000

#define CONFIG_MXC_UART

#define CONFIG_MXC_OCOTP

/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#endif

/* MMC Configs */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR      0
#define CONFIG_BOUNCE_BUFFER

/* USB Configs */
#ifdef CONFIG_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS	0

#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif

/* Networking Configs */
#ifdef CONFIG_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RGMII
#define CONFIG_ETHPRIME		"FEC"
#define CONFIG_FEC_MXC_PHYADDR		4
#define CONFIG_PHY_ATHEROS
#endif

/* Serial Flash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED	20000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#endif

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_LOADADDR	0x12000000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootcause=POR\0" \
	"bootlimit=10\0" \
	"image=/boot/fitImage\0" \
	"fdt_high=0xffffffff\0" \
	"dev=mmc\0" \
	"devnum=1\0" \
	"rootdev=mmcblk0p\0" \
	"quiet=quiet loglevel=0\0" \
	"console=" CONSOLE_DEV "\0" \
	"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
		"ro rootwait cma=128M " \
		"bootcause=${bootcause} " \
		"${quiet} console=${console} ${rtc_status} " \
		BX50V3_BOOTARGS_EXTRA "\0" \
	"doquiet=" \
		"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
			"then setenv quiet; fi\0" \
	"hasfirstboot=" \
		"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
		"/boot/bootcause/firstboot\0" \
	"swappartitions=" \
		"setexpr partnum 3 - ${partnum}\0" \
	"failbootcmd=" \
		"bx50_backlight_enable; " \
		"msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
		"echo $msg; " \
		"setenv stdout vga; " \
		"echo \"\n\n\n\n    \" $msg; " \
		"setenv stdout serial; " \
		"mw.b 0x7000A000 0xbc; " \
		"mw.b 0x7000A001 0x00; " \
		"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
	"altbootcmd=" \
		"run doquiet; " \
		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
		"run hasfirstboot || setenv partnum 0; " \
		"if test ${partnum} != 0; then " \
			"setenv bootcause REVERT; " \
			"run swappartitions loadimage doboot; " \
		"fi; " \
		"run failbootcmd\0" \
	"loadimage=" \
		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
	"doboot=" \
		"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
		"run setargs; " \
		"bootm ${loadaddr}#conf@${confidx}\0" \
	"tryboot=" \
		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
		"run loadimage || run swappartitions && run loadimage || " \
		"setenv partnum 0 && echo MISSING IMAGE;" \
		"run doboot; " \
		"run failbootcmd\0" \

#define CONFIG_MMCBOOTCOMMAND \
	"if mmc dev ${devnum}; then " \
		"run doquiet; " \
		"run tryboot; " \
	"fi; " \

#define CONFIG_USBBOOTCOMMAND \
	"echo Unsupported; " \

#ifdef CONFIG_CMD_USB
#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
#else
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
#endif

#define CONFIG_ARP_TIMEOUT     200UL

/* Miscellaneous configurable options */

#define CONFIG_SYS_MEMTEST_START       0x10000000
#define CONFIG_SYS_MEMTEST_END         0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000

#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS           1
#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR

#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* environment organization */
#define CONFIG_ENV_SIZE		(8 * 1024)
#define CONFIG_ENV_OFFSET		(768 * 1024)
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED

#ifndef CONFIG_SYS_DCACHE_OFF
#endif

#define CONFIG_SYS_FSL_USDHC_NUM	3

/* Framebuffer */
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
#define CONFIG_SYS_CONSOLE_BG_COL 0x00
#define CONFIG_HIDE_LOGO_VERSION
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CMD_BMP
#endif

#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK	66000000

#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(1, 5)

#define CONFIG_RTC_RX8010SJ
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR	0x32

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED		  100000
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3

#define CONFIG_SYS_NUM_I2C_BUSES        11
#define CONFIG_SYS_I2C_MAX_HOPS         1
#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
					{1, {I2C_NULL_HOP} }, \
					{2, {I2C_NULL_HOP} }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
					{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
				}

#define CONFIG_BCH

#endif	/* __GE_BX50V3_CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f9162b15 AB	2	/*
	3	* Copyright (C) 2015 Timesys Corporation
	4	* Copyright (C) 2015 General Electric Company
	5	* Copyright (C) 2014 Advantech
	6	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	7	*
	8	* Configuration settings for the GE MX6Q Bx50v3 boards.
f9162b15 AB	9	*/
	10
	11	#ifndef __GE_BX50V3_CONFIG_H
	12	#define __GE_BX50V3_CONFIG_H
	13
	14	#include <asm/arch/imx-regs.h>
552a848e	15	#include <asm/mach-imx/gpio.h>
f9162b15	16
3dddc793	17	#define BX50V3_BOOTARGS_EXTRA
f9162b15 AB	18	#if defined(CONFIG_TARGET_GE_B450V3)
f9162b15 AB	19	#define CONFIG_BOARD_NAME "General Electric B450v3"
f9162b15 AB	20	#elif defined(CONFIG_TARGET_GE_B650V3)
f9162b15 AB	21	#define CONFIG_BOARD_NAME "General Electric B650v3"
f9162b15 AB	22	#elif defined(CONFIG_TARGET_GE_B850V3)
f9162b15 AB	23	#define CONFIG_BOARD_NAME "General Electric B850v3"
3dddc793 KL	24	#undef BX50V3_BOOTARGS_EXTRA
	25	#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \
	26	"video=HDMI-A-1:1024x768@60 "
f9162b15 AB	27	#else
f9162b15 AB	28	#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
f9162b15 AB	29	#endif
	30
	31	#define CONFIG_MXC_UART_BASE UART3_BASE
12ca05a3	32	#define CONSOLE_DEV "ttymxc2"
f9162b15	33
f9162b15 AB	34	#define CONFIG_SUPPORT_EMMC_BOOT
f9162b15 AB	35
f9162b15 AB	36
	37	#include "mx6_common.h"
	38	#include <linux/sizes.h>
	39
f9162b15 AB	40	#define CONFIG_CMDLINE_TAG
	41	#define CONFIG_SETUP_MEMORY_TAGS
	42	#define CONFIG_INITRD_TAG
	43	#define CONFIG_REVISION_TAG
	44	#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
	45
6d656495 MW	46	#define CONFIG_HW_WATCHDOG
	47	#define CONFIG_IMX_WATCHDOG
	48	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
	49
f9162b15 AB	50	#define CONFIG_MXC_UART
f9162b15 AB	51
f9162b15 AB	52	#define CONFIG_MXC_OCOTP
	53
	54	/* SATA Configs */
aacc10c5	55	#ifdef CONFIG_CMD_SATA
f9162b15 AB	56	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	57	#define CONFIG_DWC_AHSATA_PORT_ID 0
	58	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	59	#define CONFIG_LBA48
aacc10c5	60	#endif
f9162b15 AB	61
f9162b15 AB	62	/* MMC Configs */
f9162b15 AB	63	#define CONFIG_FSL_USDHC
f9162b15 AB	64	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
f9162b15	65	#define CONFIG_BOUNCE_BUFFER
f9162b15 AB	66
f9162b15 AB	67	/* USB Configs */
fc44902a	68	#ifdef CONFIG_USB
f9162b15 AB	69	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	70	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	71	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	72	#define CONFIG_MXC_USB_FLAGS 0
f9162b15	73
f9162b15	74	#define CONFIG_USBD_HS
f9162b15	75	#define CONFIG_USB_GADGET_MASS_STORAGE
fc44902a	76	#endif
f9162b15 AB	77
f9162b15 AB	78	/* Networking Configs */
c26ffd9b	79	#ifdef CONFIG_NET
f9162b15 AB	80	#define CONFIG_FEC_MXC
	81	#define CONFIG_MII
	82	#define IMX_FEC_BASE ENET_BASE_ADDR
	83	#define CONFIG_FEC_XCV_TYPE RGMII
	84	#define CONFIG_ETHPRIME "FEC"
	85	#define CONFIG_FEC_MXC_PHYADDR 4
f9162b15	86	#define CONFIG_PHY_ATHEROS
c26ffd9b	87	#endif
f9162b15 AB	88
f9162b15 AB	89	/* Serial Flash */
f9162b15	90	#ifdef CONFIG_CMD_SF
f9162b15 AB	91	#define CONFIG_SF_DEFAULT_BUS 0
	92	#define CONFIG_SF_DEFAULT_CS 0
	93	#define CONFIG_SF_DEFAULT_SPEED 20000000
	94	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	95	#endif
	96
	97	/* allow to overwrite serial and ethaddr */
	98	#define CONFIG_ENV_OVERWRITE
f9162b15	99
f9162b15	100	#define CONFIG_LOADADDR 0x12000000
f9162b15 AB	101
f9162b15 AB	102	#define CONFIG_EXTRA_ENV_SETTINGS \
9e41b54a	103	"bootcause=POR\0" \
44395c85	104	"bootlimit=10\0" \
f07b3148	105	"image=/boot/fitImage\0" \
9e41b54a IR	106	"fdt_high=0xffffffff\0" \
	107	"dev=mmc\0" \
	108	"devnum=1\0" \
	109	"rootdev=mmcblk0p\0" \
	110	"quiet=quiet loglevel=0\0" \
12ca05a3	111	"console=" CONSOLE_DEV "\0" \
9e41b54a IR	112	"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
	113	"ro rootwait cma=128M " \
	114	"bootcause=${bootcause} " \
886678fc	115	"${quiet} console=${console} ${rtc_status} " \
3dddc793	116	BX50V3_BOOTARGS_EXTRA "\0" \
9e41b54a IR	117	"doquiet=" \
	118	"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
	119	"then setenv quiet; fi\0" \
	120	"hasfirstboot=" \
	121	"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
	122	"/boot/bootcause/firstboot\0" \
	123	"swappartitions=" \
	124	"setexpr partnum 3 - ${partnum}\0" \
	125	"failbootcmd=" \
6c0e6b45	126	"bx50_backlight_enable; " \
9e41b54a IR	127	"msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
	128	"echo $msg; " \
	129	"setenv stdout vga; " \
	130	"echo \"\n\n\n\n \" $msg; " \
	131	"setenv stdout serial; " \
	132	"mw.b 0x7000A000 0xbc; " \
	133	"mw.b 0x7000A001 0x00; " \
	134	"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
	135	"altbootcmd=" \
	136	"run doquiet; " \
	137	"setenv partnum 1; run hasfirstboot \|\| setenv partnum 2; " \
	138	"run hasfirstboot \|\| setenv partnum 0; " \
	139	"if test ${partnum} != 0; then " \
	140	"setenv bootcause REVERT; " \
	141	"run swappartitions loadimage doboot; " \
	142	"fi; " \
	143	"run failbootcmd\0" \
f9162b15 AB	144	"loadimage=" \
f9162b15 AB	145	"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
9e41b54a IR	146	"doboot=" \
9e41b54a IR	147	"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
f9162b15	148	"run setargs; " \
9e41b54a IR	149	"bootm ${loadaddr}#conf@${confidx}\0" \
	150	"tryboot=" \
	151	"setenv partnum 1; run hasfirstboot \|\| setenv partnum 2; " \
	152	"run loadimage \|\| run swappartitions && run loadimage \|\| " \
	153	"setenv partnum 0 && echo MISSING IMAGE;" \
	154	"run doboot; " \
	155	"run failbootcmd\0" \
f9162b15	156
fc44902a	157	#define CONFIG_MMCBOOTCOMMAND \
f9162b15	158	"if mmc dev ${devnum}; then " \
9e41b54a	159	"run doquiet; " \
f9162b15 AB	160	"run tryboot; " \
f9162b15 AB	161	"fi; " \
fc44902a AS	162
fc44902a AS	163	#define CONFIG_USBBOOTCOMMAND \
f07b3148	164	"echo Unsupported; " \
f9162b15	165
fc44902a AS	166	#ifdef CONFIG_CMD_USB
	167	#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
	168	#else
	169	#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
	170	#endif
	171
f9162b15 AB	172	#define CONFIG_ARP_TIMEOUT 200UL
	173
	174	/* Miscellaneous configurable options */
f9162b15	175
f9162b15 AB	176	#define CONFIG_SYS_MEMTEST_START 0x10000000
	177	#define CONFIG_SYS_MEMTEST_END 0x10010000
	178	#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
	179
	180	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	181
f9162b15 AB	182	/* Physical Memory Map */
	183	#define CONFIG_NR_DRAM_BANKS 1
	184	#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	185
	186	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	187	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	188	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	189
	190	#define CONFIG_SYS_INIT_SP_OFFSET \
	191	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	192	#define CONFIG_SYS_INIT_SP_ADDR \
	193	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	194
e856bdcf	195	/* environment organization */
f9162b15 AB	196	#define CONFIG_ENV_SIZE (8 * 1024)
	197	#define CONFIG_ENV_OFFSET (768 * 1024)
	198	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	199	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	200	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	201	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	202	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	203
f9162b15	204	#ifndef CONFIG_SYS_DCACHE_OFF
f9162b15 AB	205	#endif
	206
	207	#define CONFIG_SYS_FSL_USDHC_NUM 3
	208
	209	/* Framebuffer */
9e41b54a	210	#define CONFIG_VIDEO
07aa030a	211	#ifdef CONFIG_VIDEO
f9162b15	212	#define CONFIG_VIDEO_IPUV3
9e41b54a IR	213	#define CONFIG_CFB_CONSOLE
	214	#define CONFIG_VGA_AS_SINGLE_DEVICE
	215	#define CONFIG_SYS_CONSOLE_FG_COL 0xFF
	216	#define CONFIG_SYS_CONSOLE_BG_COL 0x00
	217	#define CONFIG_HIDE_LOGO_VERSION
f9162b15 AB	218	#define CONFIG_IMX_HDMI
f9162b15 AB	219	#define CONFIG_IMX_VIDEO_SKIP
9e41b54a	220	#define CONFIG_CMD_BMP
07aa030a	221	#endif
f9162b15	222
54971ac6 AB	223	#define CONFIG_PWM_IMX
	224	#define CONFIG_IMX6_PWM_PER_CLK 66000000
	225
3414913c IR	226	#define CONFIG_PCI
3414913c IR	227	#define CONFIG_PCI_PNP
f9162b15 AB	228	#define CONFIG_PCI_SCAN_SHOW
	229	#define CONFIG_PCIE_IMX
	230	#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
	231	#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
f9162b15	232
886678fc NH	233	#define CONFIG_RTC_RX8010SJ
	234	#define CONFIG_SYS_RTC_BUS_NUM 2
	235	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
	236
f9162b15	237	/* I2C Configs */
f9162b15 AB	238	#define CONFIG_SYS_I2C
	239	#define CONFIG_SYS_I2C_MXC
	240	#define CONFIG_SYS_I2C_SPEED 100000
	241	#define CONFIG_SYS_I2C_MXC_I2C1
	242	#define CONFIG_SYS_I2C_MXC_I2C2
	243	#define CONFIG_SYS_I2C_MXC_I2C3
	244
87da89e8	245	#define CONFIG_SYS_NUM_I2C_BUSES 11
be2808c3 IR	246	#define CONFIG_SYS_I2C_MAX_HOPS 1
be2808c3 IR	247	#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
87da89e8 MW	248	{1, {I2C_NULL_HOP} }, \
87da89e8 MW	249	{2, {I2C_NULL_HOP} }, \
be2808c3 IR	250	{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
	251	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
	252	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
	253	{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
	254	{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
	255	{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
	256	{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
	257	{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
	258	}
	259
	260	#define CONFIG_BCH
	261
f9162b15	262	#endif /* __GE_BX50V3_CONFIG_H */