[people/ms/u-boot.git] / include / configs / gose.h

/*
 * include/configs/gose.h
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __GOSE_H
#define __GOSE_H

#undef DEBUG
#define CONFIG_R8A7793
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0x70000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE6304000
#endif

/* STACK */
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
#endif

#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK	\
	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		0x40000000
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	0x20000000

/* SCIF */

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SYS_TMU_CLK_DIV	4

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH	4
#define CONFIG_SH_I2C_DATA_LOW	5
#define CONFIG_SH_I2C_CLOCK	10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA	0x00200000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ		97500000

#endif	/* __GOSE_H */
Commit	Line	Data
6a994e5b NI	1	/*
	2	* include/configs/gose.h
	3	*
	4	* Copyright (C) 2014 Renesas Electronics Corporation
	5	*
	6	* SPDX-License-Identifier: GPL-2.0
	7	*/
	8
	9	#ifndef __GOSE_H
	10	#define __GOSE_H
	11
	12	#undef DEBUG
	13	#define CONFIG_R8A7793
1cc95f6e	14	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
6a994e5b	15
5ca6dfe6	16	#include "rcar-gen2-common.h"
6a994e5b	17
1cc95f6e	18	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
6a994e5b NI	19	#define CONFIG_SYS_TEXT_BASE 0x70000000
	20	#else
	21	#define CONFIG_SYS_TEXT_BASE 0xE6304000
	22	#endif
	23
6a994e5b	24	/* STACK */
1cc95f6e	25	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
6a994e5b NI	26	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
	27	#else
	28	#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
	29	#endif
	30
	31	#define STACK_AREA_SIZE 0xC000
	32	#define LOW_LEVEL_MERAM_STACK \
	33	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	34
	35	/* MEMORY */
5ca6dfe6 NI	36	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	37	#define RCAR_GEN2_SDRAM_SIZE 0x40000000
	38	#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
6a994e5b NI	39
6a994e5b NI	40	/* SCIF */
6a994e5b NI	41
6a994e5b NI	42	/* FLASH */
6a994e5b NI	43	#define CONFIG_SPI
6a994e5b NI	44	#define CONFIG_SH_QSPI
6a994e5b	45
f0261243	46	/* SH Ether */
f0261243 NI	47	#define CONFIG_SH_ETHER
	48	#define CONFIG_SH_ETHER_USE_PORT 0
	49	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	50	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	51	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	52	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
f0261243 NI	53	#define CONFIG_BITBANGMII
	54	#define CONFIG_BITBANGMII_MULTI
	55	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	56
6a994e5b NI	57	/* Board Clock */
	58	#define RMOBILE_XTAL_CLK 20000000u
	59	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	60	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
6a994e5b NI	61	#define CONFIG_SYS_TMU_CLK_DIV 4
	62
	63	/* I2C */
	64	#define CONFIG_SYS_I2C
	65	#define CONFIG_SYS_I2C_SH
	66	#define CONFIG_SYS_I2C_SLAVE 0x7F
	67	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
6a994e5b	68	#define CONFIG_SYS_I2C_SH_SPEED0 400000
6a994e5b	69	#define CONFIG_SYS_I2C_SH_SPEED1 400000
6a994e5b NI	70	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	71	#define CONFIG_SH_I2C_DATA_HIGH 4
	72	#define CONFIG_SH_I2C_DATA_LOW 5
	73	#define CONFIG_SH_I2C_CLOCK 10000000
	74
	75	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	76
d3ee73fc	77	/* USB */
d3ee73fc NI	78	#define CONFIG_USB_EHCI_RMOBILE
	79	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	80
8e2e5886 NI	81	/* Module stop status bits */
	82	/* INTC-RT */
	83	#define CONFIG_SMSTP0_ENA 0x00400000
	84	/* MSIF */
	85	#define CONFIG_SMSTP2_ENA 0x00002000
	86	/* INTC-SYS, IRQC */
	87	#define CONFIG_SMSTP4_ENA 0x00000180
	88	/* SCIF0 */
	89	#define CONFIG_SMSTP7_ENA 0x00200000
	90
e2abab69	91	/* SDHI */
e2abab69 NI	92	#define CONFIG_SH_SDHI_FREQ 97500000
e2abab69 NI	93
6a994e5b	94	#endif /* __GOSE_H */