]>
Commit | Line | Data |
---|---|---|
0c32d96d WD |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Thomas.Lange@corelatus.se | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
b87dfd28 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
0c32d96d WD |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * This file contains the configuration parameters for the gth2 board. | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ | |
32 | #define CONFIG_GTH2 1 | |
33 | #define CONFIG_AU1X00 1 /* alchemy series cpu */ | |
34 | ||
35 | #define CONFIG_AU1000 1 | |
36 | ||
b87dfd28 | 37 | #define CONFIG_MISC_INIT_R 1 |
0c32d96d WD |
38 | |
39 | #define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */ | |
40 | ||
41 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ | |
42 | ||
43 | #define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ | |
44 | ||
45 | #define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ | |
46 | ||
47 | #define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ | |
48 | ||
49 | #define CONFIG_BAUDRATE 115200 | |
50 | ||
51 | /* valid baudrates */ | |
52 | #define CFG_BAUDRATE_TABLE { 115200 } | |
53 | ||
54 | /* Only interrupt boot if space is pressed */ | |
55 | /* If a long serial cable is connected but */ | |
56 | /* other end is dead, garbage will be read */ | |
57 | #define CONFIG_AUTOBOOT_KEYED 1 | |
58 | #define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" | |
59 | #define CONFIG_AUTOBOOT_DELAY_STR "d" | |
60 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
61 | ||
b87dfd28 WD |
62 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
63 | #define CONFIG_BOOTARGS "panic=1" | |
0c32d96d | 64 | |
b87dfd28 | 65 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
0c32d96d | 66 | "addmisc=setenv bootargs $(bootargs) " \ |
b87dfd28 WD |
67 | "ethaddr=$(ethaddr) \0" \ |
68 | "netboot=bootp;run addmisc;bootm\0" \ | |
69 | "" | |
0c32d96d WD |
70 | |
71 | /* Boot from Compact flash partition 2 as default */ | |
72 | #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" | |
73 | ||
b87dfd28 | 74 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ |
0c32d96d | 75 | ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ |
b87dfd28 | 76 | CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ |
0c32d96d WD |
77 | CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT )) |
78 | ||
79 | #include <cmd_confdefs.h> | |
80 | ||
81 | /* | |
82 | * Miscellaneous configurable options | |
83 | */ | |
b87dfd28 WD |
84 | #define CFG_LONGHELP /* undef to save memory */ |
85 | #define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */ | |
86 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
87 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
88 | #define CFG_MAXARGS 16 /* max number of command args*/ | |
0c32d96d WD |
89 | |
90 | #define CFG_MALLOC_LEN 128*1024 | |
91 | ||
92 | #define CFG_BOOTPARAMS_LEN 128*1024 | |
93 | ||
94 | #define CFG_MHZ 500 | |
95 | ||
b87dfd28 | 96 | #define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ |
0c32d96d WD |
97 | |
98 | #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ | |
99 | ||
b87dfd28 | 100 | #define CFG_LOAD_ADDR 0x81000000 /* default load address */ |
0c32d96d WD |
101 | |
102 | #define CFG_MEMTEST_START 0x80100000 | |
103 | #define CFG_MEMTEST_END 0x83000000 | |
104 | ||
b87dfd28 | 105 | #define CONFIG_HW_WATCHDOG 1 |
0c32d96d WD |
106 | |
107 | /*----------------------------------------------------------------------- | |
108 | * FLASH and environment organization | |
109 | */ | |
110 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
111 | #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
112 | ||
113 | #define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */ | |
114 | ||
115 | /* The following #defines are needed to get flash environment right */ | |
b87dfd28 WD |
116 | #define CFG_MONITOR_BASE TEXT_BASE |
117 | #define CFG_MONITOR_LEN (192 << 10) | |
0c32d96d WD |
118 | |
119 | #define CFG_INIT_SP_OFFSET 0x400000 | |
120 | ||
121 | /* We boot from this flash, selected with dip switch */ | |
122 | #define CFG_FLASH_BASE PHYS_FLASH | |
123 | ||
124 | /* timeout values are in ticks */ | |
125 | #define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ | |
126 | #define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ | |
127 | ||
b87dfd28 | 128 | #define CFG_ENV_IS_NOWHERE 1 |
0c32d96d WD |
129 | |
130 | /* Address and size of Primary Environment Sector */ | |
131 | #define CFG_ENV_ADDR 0xB0030000 | |
132 | #define CFG_ENV_SIZE 0x10000 | |
133 | ||
134 | #define CONFIG_FLASH_16BIT | |
135 | ||
136 | #define CONFIG_NR_DRAM_BANKS 2 | |
137 | ||
138 | #define CONFIG_NET_MULTI | |
139 | ||
140 | #define CONFIG_MEMSIZE_IN_BYTES | |
141 | ||
142 | /*---ATA PCMCIA ------------------------------------*/ | |
143 | #define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ | |
144 | ||
145 | #define CFG_PCMCIA_MEM_ADDR 0x20000000 | |
146 | #define CFG_PCMCIA_IO_BASE 0x28000000 | |
147 | #define CFG_PCMCIA_ATTR_BASE 0x30000000 | |
148 | ||
149 | #define CONFIG_PCMCIA_SLOT_A | |
150 | ||
151 | #define CONFIG_ATAPI 1 | |
152 | #define CONFIG_MAC_PARTITION 1 | |
153 | ||
154 | /* We run CF in "true ide" mode or a harddrive via pcmcia */ | |
155 | #define CONFIG_IDE_PCMCIA 1 | |
156 | ||
157 | /* We only support one slot for now */ | |
158 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
159 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
160 | ||
b87dfd28 | 161 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
0c32d96d WD |
162 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
163 | ||
164 | #define CFG_ATA_IDE0_OFFSET 0 | |
165 | ||
b87dfd28 | 166 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE |
0c32d96d WD |
167 | |
168 | /* Offset for data I/O */ | |
b87dfd28 | 169 | #define CFG_ATA_DATA_OFFSET 0 |
0c32d96d | 170 | |
b87dfd28 WD |
171 | /* Offset for normal register accesses */ |
172 | #define CFG_ATA_REG_OFFSET 0 | |
0c32d96d | 173 | |
b87dfd28 WD |
174 | /* Offset for alternate registers */ |
175 | #define CFG_ATA_ALT_OFFSET 0x0200 | |
0c32d96d WD |
176 | |
177 | /*----------------------------------------------------------------------- | |
178 | * Cache Configuration | |
179 | */ | |
180 | #define CFG_DCACHE_SIZE 16384 | |
181 | #define CFG_ICACHE_SIZE 16384 | |
182 | #define CFG_CACHELINE_SIZE 32 | |
183 | ||
184 | #define GPIO_CACONFIG (1<<0) | |
185 | #define GPIO_DPACONFIG (1<<6) | |
186 | #define GPIO_ERESET (1<<11) | |
187 | #define GPIO_EEDQ (1<<17) | |
188 | #define GPIO_WDI (1<<18) | |
189 | #define GPIO_RJ1LY (1<<22) | |
190 | #define GPIO_RJ1LG (1<<23) | |
191 | #define GPIO_LEDCLK (1<<29) | |
192 | #define GPIO_LEDD (1<<30) | |
193 | #define GPIO_CPU_LED (1<<31) | |
194 | ||
195 | #endif /* __CONFIG_H */ |