[people/ms/u-boot.git] / include / configs / hcu4.h

/*
 *(C) Copyright 2005-2007 Netstal Maschinen AG
 *    Niklaus Giger (Niklaus.Giger@netstal.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_HCU4		1		/* Board is HCU4	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_405GP 1
#define CONFIG_4xx   1

#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN	(320 * 1024)	/* Reserve 320 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */


#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CFG_FLASH_BASE		0xfff80000	/* start of FLASH	*/
#define CFG_MONITOR_BASE	TEXT_BASE

/* ... with on-chip memory here (4KBytes) */
#define CFG_OCM_DATA_ADDR 0xF4000000
#define CFG_OCM_DATA_SIZE 0x00001000
/* Do not set up locked dcache as init ram. */
#undef CFG_INIT_DCACHE_CS

/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
#define CFG_TEMP_STACK_OCM 1

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* OCM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
/*
 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#undef CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
#define CONFIG_SERIAL_MULTI  1
/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD	    691200

/* Size (bytes) of interrupt driven serial port buffer.
 * Set to 0 to use polling instead of interrupts.
 * Setting to 0 will also disable RTS/CTS handshaking.
 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO

/* Set console baudrate to 9600 */
#define CONFIG_BAUDRATE		9600


#define CFG_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Flash
 *----------------------------------------------------------------------*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */

#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/

#undef	CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_IS_IN_FLASH
#undef  CFG_ENV_IS_NOWHERE

#ifdef  CFG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM configuration */
#define PROM_SIZE 	2048
#define CFG_ENV_OFFSET	 512
#define CFG_ENV_SIZE	(PROM_SIZE-CFG_ENV_OFFSET)
#endif

#ifdef CFG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		8*1024	/* 8 KB Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
 * the first internal I2C controller of the PPC440EPx
 *----------------------------------------------------------------------*/
#define CFG_SPD_BUS_NUM		0

#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

/* This is the 7bit address of the device, not including P. */
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1

/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#undef CFG_I2C_MULTI_EEPROMS


#define CONFIG_PREBOOT	"echo;"						\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME		hcu4
#define CONFIG_IPADDR		172.25.1.99
#define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP		172.25.1.3

#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"							\
	"loadaddr=0x01000000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"		\
	        "bootm\0"						\
	"rootpath=/home/diagnose/eldk/ppc_4xx\0"			\
	"bootfile=/tftpboot/hcu4/uImage\0"				\
	"load=tftp 100000 hcu4/u-boot.bin\0"				\
	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;"	\
		"cp.b 100000 FFFB0000 50000\0"			        \
	"upd=run load;run update\0"					\
	"vx_rom=hcu4/hcu4_vx_rom\0"					\
	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0"		\
	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0"	\
	""
#define CONFIG_BOOTCOMMAND	"run vx"

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR	1	/* PHY address			*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup */

#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER	16 /* Number of ethernet rx buffers & desC */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM

/* SPD EEPROM (sdram speed config) disabled */
#define CONFIG_SPD_EEPROM          1
#define SPD_EEPROM_ADDRESS      0x50

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_UART	   | \
				 CFG_POST_I2C	   | \
				 CFG_POST_CACHE	   | \
				 CFG_POST_ETHER	   | \
				 CFG_POST_SPR)

#define CFG_POST_UART_TABLE	{UART0_BASE}
#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
#undef  CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/


#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CFG_EBC_CFG	0x98400000

/* Memory Bank 0 (Flash Bank 0) initialization	*/
#define CFG_EBC_PB0AP	0x02005400
#define CFG_EBC_PB0CR	0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */

#define CFG_EBC_PB1AP	0x03041200
#define CFG_EBC_PB1CR	0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/

#define CFG_EBC_PB2AP	0x02054500
#define CFG_EBC_PB2CR	0x78018000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/

#define CFG_EBC_PB3AP	0x01840300
#define CFG_EBC_PB3CR	0x7c0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/

#define CFG_EBC_PB4AP	0x01800300
#define CFG_EBC_PB4CR	0x7e0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/

#define CFG_GPIO0_OR	0xF27FFFFF  /* GPIO value */
#define CFG_GPIO0_TCR	0x7FFE0000  /* GPIO value */
#define CFG_GPIO0_ODR	0x00E897FC  /* GPIO value */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */

/* Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/


/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF0000500

#define CFG_HUSH_PARSER                 /* use "hush" command parser    */
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
714bc55b NG	1	/*
	2	*(C) Copyright 2005-2007 Netstal Maschinen AG
	3	* Niklaus Giger (Niklaus.Giger@netstal.com)
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* hcu4.h - configuration for HCU4 board (similar to hcu5.h)
	26	***********************************************************************/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_HCU4 1 /* Board is HCU4 */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
714bc55b NG	36	#define CONFIG_405GP 1
	37	#define CONFIG_4xx 1
	38
	39	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	40
	41	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	42	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	43
	44	/*-----------------------------------------------------------------------
	45	* Base addresses -- Note these are effective addresses where the
	46	* actual resources get mapped (not physical addresses)
	47	----------------------------------------------------------------------/
4bd5036e NG	48	#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
4bd5036e NG	49	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
714bc55b NG	50
	51
	52	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	53	#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
	54	#define CFG_MONITOR_BASE TEXT_BASE
	55
	56	/* ... with on-chip memory here (4KBytes) */
	57	#define CFG_OCM_DATA_ADDR 0xF4000000
	58	#define CFG_OCM_DATA_SIZE 0x00001000
	59	/* Do not set up locked dcache as init ram. */
	60	#undef CFG_INIT_DCACHE_CS
	61
	62	/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
	63	#define CFG_TEMP_STACK_OCM 1
	64
	65	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
	66	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
	67	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
	68	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
4bd5036e	69	#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
714bc55b NG	70
	71	/*-----------------------------------------------------------------------
	72	* Serial Port
	73	----------------------------------------------------------------------/
	74	/*
	75	* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	76	* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
	77	* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
	78	* The Linux BASE_BAUD define should match this configuration.
	79	* baseBaud = cpuClock/(uartDivisor*16)
	80	* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
	81	* set Linux BASE_BAUD to 403200.
	82	*/
	83	#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
4bd5036e NG	84	#define CONFIG_SERIAL_MULTI 1
4bd5036e NG	85	/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
714bc55b NG	86	#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	87	#define CFG_BASE_BAUD 691200
	88
	89	/* Size (bytes) of interrupt driven serial port buffer.
	90	* Set to 0 to use polling instead of interrupts.
	91	* Setting to 0 will also disable RTS/CTS handshaking.
	92	*/
	93	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	94
	95	/* Set console baudrate to 9600 */
	96	#define CONFIG_BAUDRATE 9600
	97
	98
	99	#define CFG_BAUDRATE_TABLE \
	100	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	101
4bd5036e NG	102	/*-----------------------------------------------------------------------
	103	* Flash
	104	----------------------------------------------------------------------/
	105
	106	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	107	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
	108
	109	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	110
	111	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	112	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	113
714bc55b NG	114	/*-----------------------------------------------------------------------
	115	* Environment
	116	----------------------------------------------------------------------/
	117
	118	#undef CFG_ENV_IS_IN_NVRAM
4bd5036e	119	#define CFG_ENV_IS_IN_FLASH
714bc55b NG	120	#undef CFG_ENV_IS_NOWHERE
	121
	122	#ifdef CFG_ENV_IS_IN_EEPROM
	123	/* Put the environment after the SDRAM configuration */
	124	#define PROM_SIZE 2048
	125	#define CFG_ENV_OFFSET 512
	126	#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
	127	#endif
	128
	129	#ifdef CFG_ENV_IS_IN_FLASH
	130	/* Put the environment in Flash */
	131	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	132	#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
4bd5036e	133	#define CFG_ENV_SIZE 81024 / 8 KB Environment Sector */
714bc55b NG	134
	135	/* Address and size of Redundant Environment Sector */
	136	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	137	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	138	#endif
	139
	140	/*-----------------------------------------------------------------------
	141	* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
	142	* the first internal I2C controller of the PPC440EPx
	143	----------------------------------------------------------------------/
	144	#define CFG_SPD_BUS_NUM 0
	145
	146	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	147	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	148	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	149	#define CFG_I2C_SLAVE 0x7F
	150
	151	/* This is the 7bit address of the device, not including P. */
	152	#define CFG_I2C_EEPROM_ADDR 0x50
	153	#define CFG_I2C_EEPROM_ADDR_LEN 1
	154
	155	/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
	156	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	157	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	158	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	159	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	160	#undef CFG_I2C_MULTI_EEPROMS
	161
	162
	163	#define CONFIG_PREBOOT "echo;" \
	164	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	165	"echo"
	166
	167	#undef CONFIG_BOOTARGS
	168
	169	/* Setup some board specific values for the default environment variables */
	170	#define CONFIG_HOSTNAME hcu4
4bd5036e	171	#define CONFIG_IPADDR 172.25.1.99
714bc55b NG	172	#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
	173	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	174	#define CONFIG_SERVERIP 172.25.1.3
	175
	176	#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
	177
ef5b4f22	178	#define CONFIG_EXTRA_ENV_SETTINGS \
714bc55b NG	179	"netdev=eth0\0" \
	180	"loadaddr=0x01000000\0" \
	181	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	182	"nfsroot=${serverip}:${rootpath}\0" \
	183	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	184	"addip=setenv bootargs ${bootargs} " \
	185	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	186	":${hostname}:${netdev}:off panic=1\0" \
	187	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	188	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	189	"bootm\0" \
	190	"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
	191	"bootfile=/tftpboot/hcu4/uImage\0" \
ef5b4f22 NG	192	"load=tftp 100000 hcu4/u-boot.bin\0" \
ef5b4f22 NG	193	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
4bd5036e	194	"cp.b 100000 FFFB0000 50000\0" \
714bc55b	195	"upd=run load;run update\0" \
ef5b4f22 NG	196	"vx_rom=hcu4/hcu4_vx_rom\0" \
	197	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
	198	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
	199	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
714bc55b NG	200	""
	201	#define CONFIG_BOOTCOMMAND "run vx"
	202
714bc55b	203	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
714bc55b NG	204
	205	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	206	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	207
	208	#define CONFIG_MII 1 /* MII PHY management */
ef5b4f22	209	#define CONFIG_PHY_ADDR 1 /* PHY address */
714bc55b	210
4bd5036e	211	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
714bc55b NG	212
714bc55b NG	213	#define CONFIG_HAS_ETH0
4bd5036e	214	#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */
3b3bff4c SR	215
	216	/*
	217	* BOOTP options
	218	*/
	219	#define CONFIG_BOOTP_BOOTFILESIZE
	220	#define CONFIG_BOOTP_BOOTPATH
	221	#define CONFIG_BOOTP_GATEWAY
	222	#define CONFIG_BOOTP_HOSTNAME
	223
	224	/*
	225	* Command line configuration.
	226	*/
	227	#include <config_cmd_default.h>
	228
	229	#define CONFIG_CMD_ASKENV
3b3bff4c SR	230	#define CONFIG_CMD_CACHE
	231	#define CONFIG_CMD_DHCP
	232	#define CONFIG_CMD_DIAG
	233	#define CONFIG_CMD_EEPROM
	234	#define CONFIG_CMD_ELF
	235	#define CONFIG_CMD_FLASH
	236	#define CONFIG_CMD_I2C
	237	#define CONFIG_CMD_IMMAP
	238	#define CONFIG_CMD_IRQ
	239	#define CONFIG_CMD_MII
	240	#define CONFIG_CMD_NET
	241	#define CONFIG_CMD_PING
	242	#define CONFIG_CMD_REGINFO
	243	#define CONFIG_CMD_SDRAM
714bc55b NG	244
	245	/* SPD EEPROM (sdram speed config) disabled */
	246	#define CONFIG_SPD_EEPROM 1
	247	#define SPD_EEPROM_ADDRESS 0x50
	248
4bd5036e NG	249	/* POST support */
	250	#define CONFIG_POST (CFG_POST_MEMORY \| \
	251	CFG_POST_CPU \| \
	252	CFG_POST_UART \| \
	253	CFG_POST_I2C \| \
	254	CFG_POST_CACHE \| \
	255	CFG_POST_ETHER \| \
	256	CFG_POST_SPR)
	257
	258	#define CFG_POST_UART_TABLE {UART0_BASE}
	259	#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
	260	#undef CONFIG_LOGBUFFER
	261	#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
	262	#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
	263
714bc55b NG	264	/*-----------------------------------------------------------------------
	265	* Miscellaneous configurable options
	266	----------------------------------------------------------------------/
	267	#define CFG_LONGHELP /* undef to save memory */
	268	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
3b3bff4c	269	#if defined(CONFIG_CMD_KGDB)
4bd5036e	270	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
714bc55b	271	#else
4bd5036e	272	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
714bc55b NG	273	#endif
	274	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	275	#define CFG_MAXARGS 16 /* max number of command args */
	276	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	277
	278	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	279	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	280
	281
	282	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	283	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	284
	285	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	286
	287	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	288	#define CONFIG_LOOPW 1 /* enable loopw command */
714bc55b NG	289	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	290
	291	/*-----------------------------------------------------------------------
	292	* External Bus Controller (EBC) Setup
	293	*/
	294
4bd5036e	295	#define CFG_EBC_CFG 0x98400000
714bc55b	296
4bd5036e NG	297	/* Memory Bank 0 (Flash Bank 0) initialization */
	298	#define CFG_EBC_PB0AP 0x02005400
	299	#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
714bc55b	300
4bd5036e NG	301	#define CFG_EBC_PB1AP 0x03041200
4bd5036e NG	302	#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
714bc55b	303
4bd5036e NG	304	#define CFG_EBC_PB2AP 0x02054500
4bd5036e NG	305	#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
714bc55b	306
4bd5036e NG	307	#define CFG_EBC_PB3AP 0x01840300
4bd5036e NG	308	#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
714bc55b	309
4bd5036e NG	310	#define CFG_EBC_PB4AP 0x01800300
	311	#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
	312
	313	#define CFG_GPIO0_OR 0xF27FFFFF /* GPIO value */
	314	#define CFG_GPIO0_TCR 0x7FFE0000 /* GPIO value */
	315	#define CFG_GPIO0_ODR 0x00E897FC /* GPIO value */
714bc55b NG	316
	317	/*
	318	* For booting Linux, the board info and command line data
	319	* have to be in the first 8 MB of memory, since this is
	320	* the maximum mapped by the Linux kernel during initialization.
	321	*/
4bd5036e	322	#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
714bc55b NG	323
	324	/* Init Memory Controller:
	325	*
	326	* BR0/1 and OR0/1 (FLASH)
	327	*/
	328
	329	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	330	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	331
	332
	333	/* Configuration Port location */
	334	#define CONFIG_PORT_ADDR 0xF0000500
	335
714bc55b NG	336	#define CFG_HUSH_PARSER /* use "hush" command parser */
714bc55b NG	337	#ifdef CFG_HUSH_PARSER
35d22f95	338	#define CFG_PROMPT_HUSH_PS2 "> "
714bc55b NG	339	#endif
714bc55b NG	340
3b3bff4c	341	#if defined(CONFIG_CMD_KGDB)
714bc55b NG	342	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	343	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	344	#endif
4bd5036e NG	345
	346	/* pass open firmware flat tree */
	347	#define CONFIG_OF_LIBFDT 1
	348	#define CONFIG_OF_BOARD_SETUP 1
	349
714bc55b	350	#endif /* __CONFIG_H */