[people/ms/u-boot.git] / include / configs / hermes.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
#define CONFIG_HERMES		1	/* ...on a HERMES-PRO board	*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; " 								\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_COMMANDS		CONFIG_CMD_DFL

#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT

/*----------------------------------------------------------------------*/

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*----------------------------------------------------------------------*/

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_ALLOC_DPRAM		1	/* use allocation routines 	*/
/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000	/* Non-Standard value!	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFE000000
#ifdef	DEBUG
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 * +0x0004
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * +0x0000 => 0x000000C0
 */
#define CFG_SIUMCR	0

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 * +0x0200 => 0x00C2
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 * +0x0240 => 0x0082
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* +0x0286 => 0x00B0D0C0 */
#define CFG_PLPRCR							\
		(	(11 << PLPRCR_MF_SHIFT) |			\
			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* +0x0282 => 0x03800000 */
#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* +0x0220 => 0x00C3 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* +0x09C4 => TIMEP=1 */
#define CFG_RCCR 0x0100

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CFG_RMDS 0

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CFG_DER	0x2002000F*/
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/

/* used to re-map FLASH
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* allow for max 4 MB of Flash */
#define CFG_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
				 OR_SCY_5_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
/* 8 bit, bank valid */
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR1/OR1 - SDRAM
 *
 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CFG_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
 */
#define HPRO2_BASE		0xE0000000
#define HPRO2_OR_AM		0xFFFF8000
#define HPRO2_TIMING		0x00000934

#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
#define CFG_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3/OR3: not used
 * BR4/OR4: not used
 * BR5/OR5: not used
 * BR6/OR6: not used
 * BR7/OR7: not used
 */

/*
 * MAMR settings for SDRAM
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e0648062 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
	37	#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
	38
	39	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	40	#undef CONFIG_8xx_CONS_SMC2
	41	#undef CONFIG_8xx_CONS_NONE
	42	#define CONFIG_BAUDRATE 9600
	43	#if 0
	44	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	45	#else
	46	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	47	#endif
	48
	49	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	50
	51	#define CONFIG_BOARD_TYPES 1 /* support board types */
	52
	53	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	54
	55	#undef CONFIG_BOOTARGS
	56	#define CONFIG_BOOTCOMMAND \
	57	"bootp; " \
	58	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	59	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	60	"bootm"
	61
	62	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	63	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	64
65	#undef CONFIG_WATCHDOG /* watchdog disabled */
66
67	#define CONFIG_COMMANDS CONFIG_CMD_DFL
68
69	#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
70
71	/----------------------------------------------------------------------/
72
73	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74	#include <cmd_confdefs.h>
75
76	/----------------------------------------------------------------------/
77
78	/*
79	* Miscellaneous configurable options
80	*/
81	#define CFG_LONGHELP /* undef to save memory */
82	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
83	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
84	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
85	#else
86	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
87	#endif
88	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
89	#define CFG_MAXARGS 16 /* max number of command args */
90	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
91
92	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
93	#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
94
95	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
96
97	#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
98
99	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
100
101	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
102
103	#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
104	/*
105	* Low Level Configuration Settings
106	* (address mappings, register initial values, etc.)
107	* You should know what you are doing if you make changes here.
108	*/
109	/*-----------------------------------------------------------------------
110	* Internal Memory Mapped Register
111	*/
112	#define CFG_IMMR 0xFF000000 /* Non-Standard value! */
113
114	/*-----------------------------------------------------------------------
115	* Definitions for initial stack pointer and data area (in DPRAM)
116	*/
117	#define CFG_INIT_RAM_ADDR CFG_IMMR
118	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
119	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
120	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
121	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
122
123	/*-----------------------------------------------------------------------
124	* Start addresses for the final memory configuration
125	* (Set up by the startup code)
126	* Please note that CFG_SDRAM_BASE _must_ start at 0
127	*/
128	#define CFG_SDRAM_BASE 0x00000000
129	#define CFG_FLASH_BASE 0xFE000000
130	#ifdef DEBUG
131	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
132	#else
133	#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
134	#endif
135	#define CFG_MONITOR_BASE CFG_FLASH_BASE
136	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
137
138	/*
139	* For booting Linux, the board info and command line data
140	* have to be in the first 8 MB of memory, since this is
141	* the maximum mapped by the Linux kernel during initialization.
142	*/
143	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
144	/*-----------------------------------------------------------------------
145	* FLASH organization
146	*/
147	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
148	#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
149
150	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
151	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
152
153	#define CFG_ENV_IS_IN_FLASH 1
154	#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
155	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
156	/*-----------------------------------------------------------------------
157	* Cache Configuration
158	*/
159	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
160	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
161	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
162	#endif
163
164	/*-----------------------------------------------------------------------
165	* SYPCR - System Protection Control 11-9
166	* SYPCR can only be written once after reset!
167	*-----------------------------------------------------------------------
168	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
169	* +0x0004
170	*/
171	#if defined(CONFIG_WATCHDOG)
172	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
173	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
174	#else
175	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
176	#endif
177
178	/*-----------------------------------------------------------------------
179	* SIUMCR - SIU Module Configuration 11-6
180	*-----------------------------------------------------------------------
181	* +0x0000 => 0x000000C0
182	*/
183	#define CFG_SIUMCR 0
184
185	/*-----------------------------------------------------------------------
186	* TBSCR - Time Base Status and Control 11-26
187	*-----------------------------------------------------------------------
188	* Clear Reference Interrupt Status, Timebase freezing enabled
189	* +0x0200 => 0x00C2
190	*/
191	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
192
193	/*-----------------------------------------------------------------------
194	* PISCR - Periodic Interrupt Status and Control 11-31
195	*-----------------------------------------------------------------------
196	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
197	* +0x0240 => 0x0082
198	*/
199	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
200
201	/*-----------------------------------------------------------------------
202	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
203	*-----------------------------------------------------------------------
204	* Reset PLL lock status sticky bit, timer expired status bit and timer
205	* interrupt status bit, set PLL multiplication factor !
206	*/
207	/* +0x0286 => 0x00B0D0C0 */
208	#define CFG_PLPRCR \
209	( (11 << PLPRCR_MF_SHIFT) \| \
210	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| \
211	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
212	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
213	)
214
215	/*-----------------------------------------------------------------------
216	* SCCR - System Clock and reset Control Register 15-27
217	*-----------------------------------------------------------------------
218	* Set clock output, timebase and RTC source and divider,
219	* power management and some other internal clocks
220	*/
221	#define SCCR_MASK SCCR_EBDF11
222	/* +0x0282 => 0x03800000 */
223	#define CFG_SCCR (SCCR_COM00 \| SCCR_TBS \| \
224	SCCR_RTDIV \| SCCR_RTSEL \| \
225	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
226	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
227	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
228	SCCR_DFNH000)
229
230	/*-----------------------------------------------------------------------
231	* RTCSC - Real-Time Clock Status and Control Register 11-27
232	*-----------------------------------------------------------------------
233	*/
234	/* +0x0220 => 0x00C3 */
235	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
236
237
238	/*-----------------------------------------------------------------------
239	* RCCR - RISC Controller Configuration Register 19-4
240	*-----------------------------------------------------------------------
241	*/
242	/* +0x09C4 => TIMEP=1 */
243	#define CFG_RCCR 0x0100
244
245	/*-----------------------------------------------------------------------
246	* RMDS - RISC Microcode Development Support Control Register
247	*-----------------------------------------------------------------------
248	*/
249	#define CFG_RMDS 0
250
251	/*-----------------------------------------------------------------------
252	*
253	*-----------------------------------------------------------------------
254	*
255	*/
256	/#define CFG_DER 0x2002000F/
257	#define CFG_DER 0
258
259	/*
260	* Init Memory Controller:
261	*
262	* BR0 and OR0 (FLASH)
263	*/
264
265	#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
266
267	/* used to re-map FLASH
268	* restrict access enough to keep SRAM working (if any)
269	* but not too much to meddle with FLASH accesses
270	*/
271	/* allow for max 4 MB of Flash */
272	#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
273	#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
274
275	/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
276	#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM \| /OR_ACS_DIV4 \|/ OR_BI \| \
277	OR_SCY_5_CLK \| OR_TRLX)
278
279	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
280	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
281	/* 8 bit, bank valid */
282	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
283
284	/*
285	* BR1/OR1 - SDRAM
286	*
287	* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
288	*/
289	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
290	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
291	#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
292
293	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
294
295	#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING )
296	#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
297
298	/*
299	* BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
300	*/
301	#define HPRO2_BASE 0xE0000000
302	#define HPRO2_OR_AM 0xFFFF8000
303	#define HPRO2_TIMING 0x00000934
304
305	#define CFG_OR2 (HPRO2_OR_AM \| HPRO2_TIMING)
306	#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
307
308	/*
309	* BR3/OR3: not used
310	* BR4/OR4: not used
311	* BR5/OR5: not used
312	* BR6/OR6: not used
313	* BR7/OR7: not used
314	*/
315
316	/*
317	* MAMR settings for SDRAM
318	*/
319
320	/* periodic timer for refresh */
321	#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
322
323	/* 8 column SDRAM */
324	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
325	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
326	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
327	/* 9 column SDRAM */
328	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
329	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
330	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
331
332	/*
333	* Internal Definitions
334	*
335	* Boot Flags
336	*/
337	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
338	#define BOOTFLAG_WARM 0x02 /* Software reboot */
339
340	#endif /* __CONFIG_H */