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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
37fc0ed2 RH |
2 | /* |
3 | * Copyright 2010-2011 Calxeda, Inc. | |
37fc0ed2 RH |
4 | */ |
5 | ||
6 | #ifndef __CONFIG_H | |
7 | #define __CONFIG_H | |
8 | ||
37fc0ed2 RH |
9 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) |
10 | ||
9df1bd41 RH |
11 | #define CONFIG_SYS_TIMER_RATE (150000000/256) |
12 | #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) | |
13 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
14 | ||
37fc0ed2 RH |
15 | /* |
16 | * Size of malloc() pool | |
17 | */ | |
18 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
19 | ||
37fc0ed2 RH |
20 | #define CONFIG_PL011_CLOCK 150000000 |
21 | #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } | |
37fc0ed2 | 22 | |
0044c42e | 23 | #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ |
877012df | 24 | |
37fc0ed2 RH |
25 | #define CONFIG_SCSI_AHCI_PLAT |
26 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 | |
27 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
28 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
29 | CONFIG_SYS_SCSI_MAX_LUN) | |
30 | ||
9a420986 RH |
31 | #define CONFIG_CALXEDA_XGMAC |
32 | ||
37fc0ed2 RH |
33 | /* |
34 | * Command line configuration. | |
35 | */ | |
37fc0ed2 | 36 | |
e1df283c RH |
37 | #define CONFIG_BOOT_RETRY_TIME -1 |
38 | #define CONFIG_RESET_TO_RETRY | |
d126e016 | 39 | |
37fc0ed2 RH |
40 | /* |
41 | * Miscellaneous configurable options | |
42 | */ | |
185a5bb0 | 43 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
37fc0ed2 | 44 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
37fc0ed2 RH |
45 | |
46 | #define CONFIG_SYS_LOAD_ADDR 0x800000 | |
185a5bb0 RH |
47 | #define CONFIG_SYS_64BIT_LBA |
48 | ||
37fc0ed2 RH |
49 | /*----------------------------------------------------------------------- |
50 | * Physical Memory Map | |
32b4a8a2 | 51 | * The DRAM is already setup, so do not touch the DT node later. |
37fc0ed2 | 52 | */ |
37fc0ed2 RH |
53 | #define PHYS_SDRAM_1_SIZE (4089 << 20) |
54 | #define CONFIG_SYS_MEMTEST_START 0x100000 | |
55 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) | |
56 | ||
a34e8549 JH |
57 | /* Environment data setup |
58 | */ | |
a34e8549 JH |
59 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ |
60 | #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ | |
37fc0ed2 RH |
61 | |
62 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
37fc0ed2 RH |
63 | #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 |
64 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
65 | ||
66 | #endif |