[thirdparty/u-boot.git] / include / configs / hrcon.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2014
 * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */

#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of one chip NT5TU64M16HG from NANYA
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_BANK_BIT_3 \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00260802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
				| (9 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26279222 */
#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x021848c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x08240100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_16)
				/* 0x43100000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0242 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=4, AL=0 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#if 1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
#endif

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */


#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

#define CONFIG_SYS_FPGA_DONE(k)		0x0010

#define CONFIG_SYS_FPGA_COUNT		1

#define CONFIG_SYS_MCLINK_MAX		3

#define CONFIG_SYS_FPGA_PTR \
	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* Pass open firmware flat tree */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

#define CONFIG_PCA953X			/* NXP PCA9554 */
#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2
#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
#define CONFIG_SYS_I2C_IHS_CH3
#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F

#ifdef CONFIG_HRCON_DH
#define CONFIG_SYS_I2C_IHS_DUAL
#define CONFIG_SYS_I2C_IHS_CH0_1
#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH1_1
#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2_1
#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH3_1
#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
#endif

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
#define I2C_SOFT_DECLARATIONS3
#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
#define I2C_SOFT_DECLARATIONS5
#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
#define I2C_SOFT_DECLARATIONS6
#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
#define I2C_SOFT_DECLARATIONS7
#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
#define I2C_SOFT_DECLARATIONS8
#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F

#ifdef CONFIG_HRCON_DH
#define I2C_SOFT_DECLARATIONS9
#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
#define I2C_SOFT_DECLARATIONS10
#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
#define I2C_SOFT_DECLARATIONS11
#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
#define I2C_SOFT_DECLARATIONS12
#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
#endif

#ifdef CONFIG_HRCON_DH
#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
#define CONFIG_HRCON_FANS			{ {10, 0x4c}, {11, 0x4c}, \
						  {12, 0x4c} }
#else
#define CONFIG_SYS_ICS8N3QV01_I2C		{9, 10, 11, 12}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_HRCON_FANS			{ {6, 0x4c}, {7, 0x4c}, \
						  {8, 0x4c} }
#endif

#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
void fpga_control_set(unsigned int bus, int pin);
void fpga_control_clear(unsigned int bus, int pin);
#endif

#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)

#ifdef CONFIG_HRCON_DH
#define I2C_ACTIVE \
	do { \
		if (I2C_ADAP_HWNR > 7) \
			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
		else \
			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
	} while (0)
#else
#define I2C_ACTIVE	{ }
#endif
#define I2C_TRISTATE	{ }
#define I2C_READ \
	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
#define I2C_SDA(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
	} while (0)
#define I2C_SCL(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
	} while (0)
#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */

/*
 * Software (bit-bang) MII driver configuration
 */
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI

/*
 * OSD Setup
 */
#define CONFIG_SYS_OSD_SCREENS		1
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */

#ifdef CONFIG_HRCON_DH
#define CONFIG_SYS_OSD_DH
#endif

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#if 1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
#else
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */


#define CONFIG_HOSTNAME		"hrcon"
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS1\0"						\
	"u-boot=u-boot.bin\0"						\
	"kernel_addr=1000000\0"					\
	"fdt_addr=C00000\0"						\
	"fdtfile=hrcon.dtb\0"				\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp ${kernel_addr} $bootfile;"				\
	"tftp ${fdt_addr} $fdtfile;"					\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_MMCBOOTCOMMAND						\
	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
	"console=$consoledev,$baudrate $othbootargs;"			\
	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
50dcf89d DE	2	/*
50dcf89d DE	3	* (C) Copyright 2014
d38826a3	4	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
50dcf89d	5	*
50dcf89d DE	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
	14	#define CONFIG_E300 1 /* E300 family */
50dcf89d	15
50dcf89d	16	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
50dcf89d	17
50dcf89d DE	18	/*
	19	* SERDES
	20	*/
	21	#define CONFIG_FSL_SERDES
	22	#define CONFIG_FSL_SERDES1 0xe3000
	23
50dcf89d DE	24	/*
	25	* DDR Setup
	26	*/
8a81bfd2	27	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
50dcf89d DE	28	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	29	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
	30	\| DDRCDR_PZ_LOZ \
	31	\| DDRCDR_NZ_LOZ \
	32	\| DDRCDR_ODT \
	33	\| DDRCDR_Q_DRN)
	34	/* 0x7b880001 */
	35	/*
	36	* Manually set up DDR parameters
	37	* consist of one chip NT5TU64M16HG from NANYA
	38	*/
	39
	40	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
	41
	42	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
	43	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	44	\| CSCONFIG_ODT_RD_NEVER \
	45	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
	46	\| CSCONFIG_BANK_BIT_3 \
	47	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
	48	/* 0x80010102 */
	49	#define CONFIG_SYS_DDR_TIMING_3 0
	50	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	51	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	52	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	53	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	54	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	55	\| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	56	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	57	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	58	/* 0x00260802 */
	59	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	60	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	61	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	62	\| (7 << TIMING_CFG1_CASLAT_SHIFT) \
	63	\| (9 << TIMING_CFG1_REFREC_SHIFT) \
	64	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	65	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	66	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	67	/* 0x26279222 */
	68	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	69	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	70	\| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	71	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	72	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	73	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	74	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
	75	/* 0x021848c5 */
	76	#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
	77	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	78	/* 0x08240100 */
	79	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	80	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
	81	\| SDRAM_CFG_DBW_16)
	82	/* 0x43100000 */
	83
	84	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
	85	#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
	86	\| (0x0242 << SDRAM_MODE_SD_SHIFT))
	87	/* ODT 150ohm CL=4, AL=0 on SDRAM */
	88	#define CONFIG_SYS_DDR_MODE2 0x00000000
	89
	90	/*
	91	* Memory test
92	*/
93	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
94	#define CONFIG_SYS_MEMTEST_END 0x07f00000
95
96	/*
97	* The reserved memory
98	*/
99	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
100
101	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
102	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
103
104	/*
105	* Initial RAM Base Address Setup
106	*/
107	#define CONFIG_SYS_INIT_RAM_LOCK 1
108	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
109	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
110	#define CONFIG_SYS_GBL_DATA_OFFSET \
111	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
112
50dcf89d DE	113	/*
	114	* FLASH on the Local Bus
	115	*/
	116	#if 1
50dcf89d DE	117	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	118	#define CONFIG_FLASH_CFI_LEGACY
	119	#define CONFIG_SYS_FLASH_LEGACY_512Kx16
50dcf89d DE	120	#endif
	121
	122	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	123	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
50dcf89d	124
50dcf89d DE	125
	126	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	127	#define CONFIG_SYS_MAX_FLASH_SECT 135
	128
	129	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	130	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	131
50dcf89d DE	132	#define CONFIG_SYS_FPGA_DONE(k) 0x0010
	133
	134	#define CONFIG_SYS_FPGA_COUNT 1
	135
	136	#define CONFIG_SYS_MCLINK_MAX 3
	137
	138	#define CONFIG_SYS_FPGA_PTR \
	139	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
	140
	141	/*
	142	* Serial Port
	143	*/
50dcf89d DE	144	#define CONFIG_SYS_NS16550_SERIAL
	145	#define CONFIG_SYS_NS16550_REG_SIZE 1
	146	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	147
	148	#define CONFIG_SYS_BAUDRATE_TABLE \
	149	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	150
	151	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	152	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	153
50dcf89d	154	/* Pass open firmware flat tree */
50dcf89d DE	155
	156	/* I2C */
	157	#define CONFIG_SYS_I2C
	158	#define CONFIG_SYS_I2C_FSL
	159	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	160	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	161	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	162
	163	#define CONFIG_PCA953X /* NXP PCA9554 */
	164	#define CONFIG_PCA9698 /* NXP PCA9698 */
	165
	166	#define CONFIG_SYS_I2C_IHS
	167	#define CONFIG_SYS_I2C_IHS_CH0
	168	#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
	169	#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
	170	#define CONFIG_SYS_I2C_IHS_CH1
	171	#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
	172	#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
	173	#define CONFIG_SYS_I2C_IHS_CH2
	174	#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
	175	#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
	176	#define CONFIG_SYS_I2C_IHS_CH3
	177	#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
	178	#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
	179
7ed45d3d DE	180	#ifdef CONFIG_HRCON_DH
	181	#define CONFIG_SYS_I2C_IHS_DUAL
	182	#define CONFIG_SYS_I2C_IHS_CH0_1
	183	#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
	184	#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
	185	#define CONFIG_SYS_I2C_IHS_CH1_1
	186	#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
	187	#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
	188	#define CONFIG_SYS_I2C_IHS_CH2_1
	189	#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
	190	#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
	191	#define CONFIG_SYS_I2C_IHS_CH3_1
	192	#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
	193	#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
	194	#endif
	195
50dcf89d DE	196	/*
	197	* Software (bit-bang) I2C driver configuration
	198	*/
	199	#define CONFIG_SYS_I2C_SOFT
	200	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	201	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
	202	#define I2C_SOFT_DECLARATIONS2
	203	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
	204	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
	205	#define I2C_SOFT_DECLARATIONS3
	206	#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
	207	#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
	208	#define I2C_SOFT_DECLARATIONS4
	209	#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
	210	#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
7ed45d3d DE	211	#define I2C_SOFT_DECLARATIONS5
	212	#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
	213	#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
	214	#define I2C_SOFT_DECLARATIONS6
	215	#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
	216	#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
	217	#define I2C_SOFT_DECLARATIONS7
	218	#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
	219	#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
	220	#define I2C_SOFT_DECLARATIONS8
	221	#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
	222	#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
5c3b6dc1 DE	223
	224	#ifdef CONFIG_HRCON_DH
	225	#define I2C_SOFT_DECLARATIONS9
	226	#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
	227	#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
	228	#define I2C_SOFT_DECLARATIONS10
	229	#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
	230	#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
	231	#define I2C_SOFT_DECLARATIONS11
	232	#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
	233	#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
	234	#define I2C_SOFT_DECLARATIONS12
	235	#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
	236	#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
7ed45d3d DE	237	#endif
	238
	239	#ifdef CONFIG_HRCON_DH
5c3b6dc1	240	#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
7ed45d3d	241	#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
5c3b6dc1 DE	242	#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
5c3b6dc1 DE	243	{12, 0x4c} }
7ed45d3d	244	#else
5c3b6dc1	245	#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
50dcf89d	246	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
5c3b6dc1 DE	247	#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
5c3b6dc1 DE	248	{8, 0x4c} }
7ed45d3d	249	#endif
50dcf89d DE	250
	251	#ifndef __ASSEMBLY__
	252	void fpga_gpio_set(unsigned int bus, int pin);
	253	void fpga_gpio_clear(unsigned int bus, int pin);
	254	int fpga_gpio_get(unsigned int bus, int pin);
7ed45d3d DE	255	void fpga_control_set(unsigned int bus, int pin);
7ed45d3d DE	256	void fpga_control_clear(unsigned int bus, int pin);
50dcf89d DE	257	#endif
50dcf89d DE	258
5c3b6dc1 DE	259	#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
	260	#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
	261	#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
	262
7ed45d3d DE	263	#ifdef CONFIG_HRCON_DH
	264	#define I2C_ACTIVE \
	265	do { \
5c3b6dc1 DE	266	if (I2C_ADAP_HWNR > 7) \
5c3b6dc1 DE	267	fpga_control_set(I2C_FPGA_IDX, 0x0004); \
7ed45d3d	268	else \
5c3b6dc1	269	fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
7ed45d3d DE	270	} while (0)
7ed45d3d DE	271	#else
50dcf89d	272	#define I2C_ACTIVE { }
7ed45d3d	273	#endif
50dcf89d DE	274	#define I2C_TRISTATE { }
50dcf89d DE	275	#define I2C_READ \
5c3b6dc1	276	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
50dcf89d DE	277	#define I2C_SDA(bit) \
	278	do { \
	279	if (bit) \
5c3b6dc1	280	fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
50dcf89d	281	else \
5c3b6dc1	282	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
50dcf89d DE	283	} while (0)
	284	#define I2C_SCL(bit) \
	285	do { \
	286	if (bit) \
5c3b6dc1	287	fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
50dcf89d	288	else \
5c3b6dc1	289	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
50dcf89d DE	290	} while (0)
	291	#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
	292
	293	/*
	294	* Software (bit-bang) MII driver configuration
	295	*/
	296	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	297	#define CONFIG_BITBANGMII_MULTI
	298
	299	/*
	300	* OSD Setup
	301	*/
	302	#define CONFIG_SYS_OSD_SCREENS 1
	303	#define CONFIG_SYS_DP501_DIFFERENTIAL
	304	#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
	305
7ed45d3d DE	306	#ifdef CONFIG_HRCON_DH
	307	#define CONFIG_SYS_OSD_DH
	308	#endif
	309
50dcf89d DE	310	/*
	311	* General PCI
	312	* Addresses are mapped 1-1.
	313	*/
	314	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	315	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	316	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	317	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	318	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	319	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	320	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	321	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	322	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	323
	324	/* enable PCIE clock */
	325	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
	326
50dcf89d DE	327	#define CONFIG_PCI_INDIRECT_BRIDGE
	328	#define CONFIG_PCIE
	329
50dcf89d DE	330	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	331	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
	332
	333	/*
	334	* TSEC
	335	*/
50dcf89d DE	336	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	337	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	338
	339	/*
	340	* TSEC ethernet configuration
	341	*/
50dcf89d DE	342	#define CONFIG_TSEC1
	343	#define CONFIG_TSEC1_NAME "eTSEC0"
	344	#define TSEC1_PHY_ADDR 1
	345	#define TSEC1_PHYIDX 0
	346	#define TSEC1_FLAGS TSEC_GIGABIT
	347
	348	/* Options are: eTSEC[0-1] */
	349	#define CONFIG_ETHPRIME "eTSEC0"
	350
	351	/*
	352	* Environment
	353	*/
	354	#if 1
50dcf89d DE	355	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	356	CONFIG_SYS_MONITOR_LEN)
	357	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	358	#define CONFIG_ENV_SIZE 0x2000
	359	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	360	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	361	#else
50dcf89d DE	362	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	363	#endif
	364
	365	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	366	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	367
	368	/*
	369	* Command line configuration.
	370	*/
50dcf89d	371
50dcf89d DE	372	/*
	373	* Miscellaneous configurable options
	374	*/
50dcf89d	375	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
50dcf89d DE	376	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
50dcf89d DE	377
50dcf89d DE	378	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
50dcf89d DE	379
50dcf89d DE	380	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	381
	382	/*
	383	* For booting Linux, the board info and command line data
	384	* have to be in the first 256 MB of memory, since this is
	385	* the maximum mapped by the Linux kernel during initialization.
	386	*/
	387	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
	388
50dcf89d DE	389	/*
	390	* Environment Configuration
	391	*/
	392
	393	#define CONFIG_ENV_OVERWRITE
	394
	395	#if defined(CONFIG_TSEC_ENET)
	396	#define CONFIG_HAS_ETH0
	397	#endif
	398
50dcf89d DE	399	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
50dcf89d DE	400
50dcf89d	401
5bc0543d	402	#define CONFIG_HOSTNAME "hrcon"
50dcf89d DE	403	#define CONFIG_ROOTPATH "/opt/nfsroot"
	404	#define CONFIG_BOOTFILE "uImage"
	405
50dcf89d DE	406	#define CONFIG_EXTRA_ENV_SETTINGS \
	407	"netdev=eth0\0" \
	408	"consoledev=ttyS1\0" \
	409	"u-boot=u-boot.bin\0" \
	410	"kernel_addr=1000000\0" \
	411	"fdt_addr=C00000\0" \
	412	"fdtfile=hrcon.dtb\0" \
	413	"load=tftp ${loadaddr} ${u-boot}\0" \
	414	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	415	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
	416	" +${filesize};cp.b ${fileaddr} " \
	417	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
	418	"upd=run load update\0" \
	419
	420	#define CONFIG_NFSBOOTCOMMAND \
	421	"setenv bootargs root=/dev/nfs rw " \
	422	"nfsroot=$serverip:$rootpath " \
	423	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	424	"console=$consoledev,$baudrate $othbootargs;" \
	425	"tftp ${kernel_addr} $bootfile;" \
	426	"tftp ${fdt_addr} $fdtfile;" \
	427	"bootm ${kernel_addr} - ${fdt_addr}"
	428
	429	#define CONFIG_MMCBOOTCOMMAND \
	430	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
	431	"console=$consoledev,$baudrate $othbootargs;" \
	432	"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
	433	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
	434	"bootm ${kernel_addr} - ${fdt_addr}"
	435
	436	#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
	437
50dcf89d	438	#endif /* __CONFIG_H */