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eaf8c986 HS |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * Based on: | |
6 | * Copyright (c) 2011 IDS GmbH, Germany | |
7 | * Sergej Stepanov <ste@ids.de> | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_MPC831x | |
19 | #define CONFIG_MPC8313 | |
20 | #define CONFIG_IDS8313 | |
21 | ||
22 | #define CONFIG_FSL_ELBC | |
23 | ||
24 | #define CONFIG_MISC_INIT_R | |
25 | ||
eaf8c986 HS |
26 | #define CONFIG_BOOT_RETRY_TIME 900 |
27 | #define CONFIG_BOOT_RETRY_MIN 30 | |
eaf8c986 HS |
28 | #define CONFIG_RESET_TO_RETRY |
29 | ||
30 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
31 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
32 | ||
33 | #define CONFIG_SYS_IMMR 0xF0000000 | |
34 | ||
35 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
36 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
37 | ||
38 | /* | |
39 | * Hardware Reset Configuration Word | |
40 | * if CLKIN is 66.000MHz, then | |
41 | * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz | |
42 | */ | |
43 | #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ | |
44 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
45 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
46 | HRCWL_CORE_TO_CSB_2X1) | |
47 | ||
48 | #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ | |
49 | HRCWH_CORE_ENABLE |\ | |
50 | HRCWH_FROM_0XFFF00100 |\ | |
51 | HRCWH_BOOTSEQ_DISABLE |\ | |
52 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
53 | HRCWH_ROM_LOC_LOCAL_8BIT |\ | |
54 | HRCWH_RL_EXT_LEGACY |\ | |
55 | HRCWH_TSEC1M_IN_MII |\ | |
56 | HRCWH_TSEC2M_IN_MII |\ | |
57 | HRCWH_BIG_ENDIAN) | |
58 | ||
59 | #define CONFIG_SYS_SICRH 0x00000000 | |
60 | #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) | |
61 | ||
62 | #define CONFIG_HWCONFIG | |
63 | ||
64 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
65 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ | |
66 | HID0_ENABLE_INSTRUCTION_CACHE |\ | |
67 | HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) | |
68 | ||
69 | #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) | |
70 | ||
71 | /* | |
72 | * Definitions for initial stack pointer and data area (in DCACHE ) | |
73 | */ | |
74 | #define CONFIG_SYS_INIT_RAM_LOCK | |
75 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 | |
76 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ | |
77 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 | |
78 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ | |
79 | - CONFIG_SYS_GBL_DATA_SIZE) | |
80 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
81 | ||
82 | /* | |
83 | * Local Bus LCRR and LBCR regs | |
84 | */ | |
85 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 | |
86 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
87 | #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ | |
88 | (0xFF << LBCR_BMT_SHIFT) |\ | |
89 | 0xF) | |
90 | ||
91 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
92 | ||
93 | /* | |
94 | * Internal Definitions | |
95 | */ | |
96 | /* | |
97 | * DDR Setup | |
98 | */ | |
99 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
100 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
101 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
102 | ||
103 | /* | |
104 | * Manually set up DDR parameters, | |
105 | * as this board has not the SPD connected to I2C. | |
106 | */ | |
107 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ | |
108 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ | |
109 | 0x00010000 |\ | |
110 | CSCONFIG_ROW_BIT_13 |\ | |
111 | CSCONFIG_COL_BIT_10) | |
112 | ||
113 | #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ | |
114 | CSCONFIG_BANK_BIT_3) | |
115 | ||
116 | #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ | |
117 | #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ | |
118 | (3 << TIMING_CFG0_WRT_SHIFT) |\ | |
119 | (3 << TIMING_CFG0_RRT_SHIFT) |\ | |
120 | (3 << TIMING_CFG0_WWT_SHIFT) |\ | |
121 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ | |
122 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ | |
123 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ | |
124 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
125 | #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ | |
126 | (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ | |
127 | (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ | |
128 | (7 << TIMING_CFG1_CASLAT_SHIFT) |\ | |
129 | (4 << TIMING_CFG1_REFREC_SHIFT) |\ | |
130 | (4 << TIMING_CFG1_WRREC_SHIFT) |\ | |
131 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ | |
132 | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
133 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ | |
134 | (5 << TIMING_CFG2_CPO_SHIFT) |\ | |
135 | (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ | |
136 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ | |
137 | (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ | |
138 | (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ | |
139 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
140 | ||
141 | #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ | |
142 | (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
143 | ||
144 | #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ | |
145 | SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ | |
146 | SDRAM_CFG_DBW_32 |\ | |
147 | SDRAM_CFG_SDRAM_TYPE_DDR2) | |
148 | ||
149 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 | |
150 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ | |
151 | (0x0242 << SDRAM_MODE_SD_SHIFT)) | |
152 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
153 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 | |
154 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ | |
155 | DDRCDR_PZ_NOMZ |\ | |
156 | DDRCDR_NZ_NOMZ |\ | |
157 | DDRCDR_ODT |\ | |
158 | DDRCDR_M_ODR |\ | |
159 | DDRCDR_Q_DRN) | |
160 | ||
161 | /* | |
162 | * on-board devices | |
163 | */ | |
164 | #define CONFIG_TSEC1 | |
165 | #define CONFIG_TSEC2 | |
166 | #define CONFIG_TSEC_ENET | |
eaf8c986 HS |
167 | #define CONFIG_HARD_SPI |
168 | #define CONFIG_HARD_I2C | |
169 | ||
170 | /* | |
171 | * NOR FLASH setup | |
172 | */ | |
173 | #define CONFIG_SYS_FLASH_CFI | |
174 | #define CONFIG_FLASH_CFI_DRIVER | |
175 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
176 | #define CONFIG_FLASH_SHOW_PROGRESS 50 | |
177 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
178 | ||
179 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 | |
180 | #define CONFIG_SYS_FLASH_SIZE 8 | |
181 | #define CONFIG_SYS_FLASH_PROTECTION | |
182 | ||
183 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
184 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 | |
185 | ||
186 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ | |
187 | BR_PS_8 |\ | |
188 | BR_MS_GPCM |\ | |
189 | BR_V) | |
190 | ||
191 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ | |
192 | OR_GPCM_SCY_10 |\ | |
193 | OR_GPCM_EHTR |\ | |
194 | OR_GPCM_TRLX |\ | |
195 | OR_GPCM_CSNT |\ | |
196 | OR_GPCM_EAD) | |
197 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
198 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
199 | ||
200 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 | |
201 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
202 | ||
203 | /* | |
204 | * NAND FLASH setup | |
205 | */ | |
206 | #define CONFIG_SYS_NAND_BASE 0xE1000000 | |
207 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
208 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
eaf8c986 HS |
209 | #define CONFIG_NAND_FSL_ELBC |
210 | #define CONFIG_SYS_NAND_PAGE_SIZE (2048) | |
211 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) | |
212 | #define NAND_CACHE_PAGES 64 | |
213 | ||
214 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE | |
215 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E | |
216 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM | |
217 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
218 | ||
219 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ | |
220 | (2<<BR_DECC_SHIFT) |\ | |
221 | BR_PS_8 |\ | |
222 | BR_MS_FCM |\ | |
223 | BR_V) | |
224 | ||
225 | #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ | |
226 | OR_FCM_PGS |\ | |
227 | OR_FCM_CSCT |\ | |
228 | OR_FCM_CST |\ | |
229 | OR_FCM_CHT |\ | |
230 | OR_FCM_SCY_4 |\ | |
231 | OR_FCM_TRLX |\ | |
232 | OR_FCM_EHTR |\ | |
233 | OR_FCM_RST) | |
234 | ||
235 | /* | |
236 | * MRAM setup | |
237 | */ | |
238 | #define CONFIG_SYS_MRAM_BASE 0xE2000000 | |
239 | #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ | |
240 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE | |
241 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ | |
242 | ||
243 | #define CONFIG_SYS_OR_TIMING_MRAM | |
244 | ||
245 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ | |
246 | BR_PS_8 |\ | |
247 | BR_MS_GPCM |\ | |
248 | BR_V) | |
249 | ||
250 | #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 | |
251 | ||
252 | /* | |
253 | * CPLD setup | |
254 | */ | |
255 | #define CONFIG_SYS_CPLD_BASE 0xE3000000 | |
256 | #define CONFIG_SYS_CPLD_SIZE 0x8000 | |
257 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE | |
258 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E | |
259 | ||
260 | #define CONFIG_SYS_OR_TIMING_MRAM | |
261 | ||
262 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ | |
263 | BR_PS_8 |\ | |
264 | BR_MS_GPCM |\ | |
265 | BR_V) | |
266 | ||
267 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 | |
268 | ||
269 | /* | |
270 | * HW-Watchdog | |
271 | */ | |
272 | #define CONFIG_WATCHDOG 1 | |
273 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF | |
274 | ||
275 | /* | |
276 | * I2C setup | |
277 | */ | |
eaf8c986 HS |
278 | #define CONFIG_SYS_I2C |
279 | #define CONFIG_SYS_I2C_FSL | |
280 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
281 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
282 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
283 | #define CONFIG_RTC_PCF8563 | |
284 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 | |
285 | ||
286 | /* | |
287 | * SPI setup | |
288 | */ | |
289 | #ifdef CONFIG_HARD_SPI | |
290 | #define CONFIG_MPC8XXX_SPI | |
eaf8c986 HS |
291 | #define CONFIG_SYS_GPIO1_PRELIM |
292 | #define CONFIG_SYS_GPIO1_DIR 0x00000001 | |
293 | #define CONFIG_SYS_GPIO1_DAT 0x00000001 | |
294 | #endif | |
295 | ||
296 | /* | |
297 | * Ethernet setup | |
298 | */ | |
299 | #ifdef CONFIG_TSEC1 | |
300 | #define CONFIG_HAS_ETH0 | |
301 | #define CONFIG_TSEC1_NAME "TSEC0" | |
302 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
303 | #define TSEC1_PHY_ADDR 0x1 | |
304 | #define TSEC1_FLAGS TSEC_GIGABIT | |
305 | #define TSEC1_PHYIDX 0 | |
306 | #endif | |
307 | ||
308 | #ifdef CONFIG_TSEC2 | |
309 | #define CONFIG_HAS_ETH1 | |
310 | #define CONFIG_TSEC2_NAME "TSEC1" | |
311 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
312 | #define TSEC2_PHY_ADDR 0x3 | |
313 | #define TSEC2_FLAGS TSEC_GIGABIT | |
314 | #define TSEC2_PHYIDX 0 | |
315 | #endif | |
316 | #define CONFIG_ETHPRIME "TSEC1" | |
317 | ||
318 | /* | |
319 | * Serial Port | |
320 | */ | |
321 | #define CONFIG_CONS_INDEX 1 | |
eaf8c986 HS |
322 | #define CONFIG_SYS_NS16550_SERIAL |
323 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
324 | ||
325 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
326 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
327 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
328 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
329 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) | |
330 | ||
331 | #define CONFIG_HAS_FSL_DR_USB | |
332 | #define CONFIG_SYS_SCCR_USBDRCM 3 | |
333 | ||
334 | /* | |
335 | * BAT's | |
336 | */ | |
337 | #define CONFIG_HIGH_BATS | |
338 | ||
339 | /* DDR @ 0x00000000 */ | |
340 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ | |
341 | BATL_PP_10) | |
342 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ | |
343 | BATU_BL_256M |\ | |
344 | BATU_VS |\ | |
345 | BATU_VP) | |
346 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
347 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
348 | ||
349 | /* Initial RAM @ 0xFD000000 */ | |
350 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ | |
351 | BATL_PP_10 |\ | |
352 | BATL_GUARDEDSTORAGE) | |
353 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ | |
354 | BATU_BL_256K |\ | |
355 | BATU_VS |\ | |
356 | BATU_VP) | |
357 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
358 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
359 | ||
360 | /* FLASH @ 0xFF800000 */ | |
361 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ | |
362 | BATL_PP_10 |\ | |
363 | BATL_GUARDEDSTORAGE) | |
364 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ | |
365 | BATU_BL_8M |\ | |
366 | BATU_VS |\ | |
367 | BATU_VP) | |
368 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ | |
369 | BATL_PP_10 |\ | |
370 | BATL_CACHEINHIBIT |\ | |
371 | BATL_GUARDEDSTORAGE) | |
372 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
373 | ||
374 | #define CONFIG_SYS_IBAT3L (0) | |
375 | #define CONFIG_SYS_IBAT3U (0) | |
376 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
377 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
378 | ||
379 | #define CONFIG_SYS_IBAT4L (0) | |
380 | #define CONFIG_SYS_IBAT4U (0) | |
381 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
382 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
383 | ||
384 | /* IMMRBAR @ 0xF0000000 */ | |
385 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ | |
386 | BATL_PP_10 |\ | |
387 | BATL_CACHEINHIBIT |\ | |
388 | BATL_GUARDEDSTORAGE) | |
389 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ | |
390 | BATU_BL_128M |\ | |
391 | BATU_VS |\ | |
392 | BATU_VP) | |
393 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
394 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
395 | ||
396 | /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ | |
397 | #define CONFIG_SYS_IBAT6L (0xE0000000 |\ | |
398 | BATL_PP_10 |\ | |
399 | BATL_GUARDEDSTORAGE) | |
400 | #define CONFIG_SYS_IBAT6U (0xE0000000 |\ | |
401 | BATU_BL_256M |\ | |
402 | BATU_VS |\ | |
403 | BATU_VP) | |
404 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
405 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
406 | ||
407 | #define CONFIG_SYS_IBAT7L (0) | |
408 | #define CONFIG_SYS_IBAT7U (0) | |
409 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
410 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
411 | ||
412 | /* | |
413 | * U-Boot environment setup | |
414 | */ | |
eaf8c986 | 415 | #define CONFIG_CMD_NAND |
eaf8c986 HS |
416 | #define CONFIG_CMD_DATE |
417 | #define CONFIG_CMDLINE_EDITING | |
eaf8c986 HS |
418 | #define CONFIG_CMD_JFFS2 |
419 | #define CONFIG_BOOTP_SUBNETMASK | |
420 | #define CONFIG_BOOTP_GATEWAY | |
421 | #define CONFIG_BOOTP_HOSTNAME | |
422 | #define CONFIG_BOOTP_BOOTPATH | |
423 | #define CONFIG_BOOTP_BOOTFILESIZE | |
eaf8c986 HS |
424 | |
425 | /* | |
426 | * The reserved memory | |
427 | */ | |
428 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
429 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) | |
430 | #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) | |
431 | ||
432 | /* | |
433 | * Environment Configuration | |
434 | */ | |
435 | #define CONFIG_ENV_IS_IN_FLASH | |
436 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ | |
437 | + CONFIG_SYS_MONITOR_LEN) | |
438 | #define CONFIG_ENV_SIZE 0x20000 | |
439 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) | |
440 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
441 | ||
eaf8c986 HS |
442 | #define CONFIG_NETDEV eth1 |
443 | #define CONFIG_HOSTNAME ids8313 | |
444 | #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" | |
445 | #define CONFIG_BOOTFILE "ids8313/uImage" | |
446 | #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" | |
447 | #define CONFIG_FDTFILE "ids8313/ids8313.dtb" | |
448 | #define CONFIG_LOADADDR 0x400000 | |
449 | #define CONFIG_CMD_ENV_FLAGS | |
450 | #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" | |
451 | ||
452 | #define CONFIG_BAUDRATE 115200 | |
eaf8c986 HS |
453 | |
454 | /* Initial Memory map for Linux*/ | |
455 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
456 | ||
457 | /* | |
458 | * Miscellaneous configurable options | |
459 | */ | |
460 | #define CONFIG_SYS_LONGHELP | |
eaf8c986 HS |
461 | #define CONFIG_SYS_CBSIZE 1024 |
462 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ | |
463 | + sizeof(CONFIG_SYS_PROMPT)+16) | |
464 | #define CONFIG_SYS_MAXARGS 16 | |
465 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
eaf8c986 HS |
466 | |
467 | #define CONFIG_SYS_MEMTEST_START 0x00001000 | |
468 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 | |
469 | ||
470 | #define CONFIG_SYS_LOAD_ADDR 0x100000 | |
471 | #define CONFIG_MII | |
472 | #define CONFIG_LOADS_ECHO | |
473 | #define CONFIG_TIMESTAMP | |
474 | #define CONFIG_PREBOOT "echo;" \ | |
475 | "echo Type \\\"run nfsboot\\\" " \ | |
476 | "to mount root filesystem over NFS;echo" | |
477 | #undef CONFIG_BOOTARGS | |
478 | #define CONFIG_BOOTCOMMAND "run boot_cramfs" | |
479 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
480 | ||
481 | #define CONFIG_JFFS2_NAND | |
482 | #define CONFIG_JFFS2_DEV "0" | |
483 | ||
484 | /* mtdparts command line support */ | |
485 | #define CONFIG_CMD_MTDPARTS | |
486 | #define CONFIG_FLASH_CFI_MTD | |
487 | #define CONFIG_MTD_DEVICE | |
488 | #define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash" | |
489 | #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \ | |
490 | "768k(BOOT-BIN)," \ | |
491 | "128k(BOOT-ENV),128k(BOOT-REDENV);" \ | |
492 | "e1000000.flash:-(ubi)" | |
493 | ||
494 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
495 | "netdev=" __stringify(CONFIG_NETDEV) "\0" \ | |
496 | "ethprime=TSEC1\0" \ | |
497 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
498 | "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ | |
499 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
500 | " +${filesize}; " \ | |
501 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
502 | " +${filesize}; " \ | |
503 | "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
504 | " ${filesize}; " \ | |
505 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
506 | " +${filesize}; " \ | |
507 | "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
508 | " ${filesize}\0" \ | |
509 | "console=ttyS0\0" \ | |
510 | "fdtaddr=0x780000\0" \ | |
511 | "kernel_addr=ff800000\0" \ | |
512 | "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ | |
513 | "setbootargs=setenv bootargs " \ | |
514 | "root=${rootdev} rw console=${console}," \ | |
515 | "${baudrate} ${othbootargs}\0" \ | |
516 | "setipargs=setenv bootargs root=${rootdev} rw " \ | |
517 | "nfsroot=${serverip}:${rootpath} " \ | |
518 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
519 | "${netmask}:${hostname}:${netdev}:off " \ | |
520 | "console=${console},${baudrate} ${othbootargs}\0" \ | |
521 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
522 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
523 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
524 | "\0" | |
525 | ||
526 | #define CONFIG_NFSBOOTCOMMAND \ | |
527 | "setenv rootdev /dev/nfs;" \ | |
528 | "run setipargs;run addmtd;" \ | |
529 | "tftp ${loadaddr} ${bootfile};" \ | |
530 | "tftp ${fdtaddr} ${fdtfile};" \ | |
531 | "fdt addr ${fdtaddr};" \ | |
532 | "bootm ${loadaddr} - ${fdtaddr}" | |
533 | ||
534 | /* UBI Support */ | |
535 | #define CONFIG_CMD_NAND_TRIMFFS | |
536 | #define CONFIG_CMD_UBI | |
537 | #define CONFIG_CMD_UBIFS | |
538 | #define CONFIG_RBTREE | |
539 | #define CONFIG_LZO | |
540 | #define CONFIG_MTD_PARTITIONS | |
541 | ||
542 | /* bootcount support */ | |
543 | #define CONFIG_BOOTCOUNT_LIMIT | |
544 | #define CONFIG_BOOTCOUNT_I2C | |
545 | #define CONFIG_BOOTCOUNT_ALEN 1 | |
546 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 | |
547 | ||
d835e91d | 548 | #define CONFIG_IMAGE_FORMAT_LEGACY |
eaf8c986 | 549 | #define CONFIG_CMD_HASH |
eaf8c986 HS |
550 | #define CONFIG_SHA1 |
551 | #define CONFIG_SHA256 | |
eaf8c986 HS |
552 | |
553 | #endif /* __CONFIG_H */ |