[thirdparty/u-boot.git] / include / configs / ids8313.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2013
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * Based on:
 * Copyright (c) 2011 IDS GmbH, Germany
 * Sergej Stepanov <ste@ids.de>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_FSL_ELBC

#define CONFIG_BOOT_RETRY_TIME		900
#define CONFIG_BOOT_RETRY_MIN		30
#define CONFIG_RESET_TO_RETRY

#define CONFIG_SYS_SICRH	0x00000000
#define CONFIG_SYS_SICRL	(SICRL_LBC | SICRL_SPI_D)

#define CONFIG_HWCONFIG

/*
 * Definitions for initial stack pointer and data area (in DCACHE )
 */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000  /* End of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_SIZE	0x100
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
					 - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Internal Definitions
 */
/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000

/*
 * Manually set up DDR parameters,
 * as this board has not the SPD connected to I2C.
 */
#define CONFIG_SYS_DDR_SIZE		256		/* MB */
#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN |\
					 0x00010000 |\
					 CSCONFIG_ROW_BIT_13 |\
					 CSCONFIG_COL_BIT_10)

#define CONFIG_SYS_DDR_CONFIG_256	(CONFIG_SYS_DDR_CONFIG | \
					 CSCONFIG_BANK_BIT_3)

#define CONFIG_SYS_DDR_TIMING_3	(1 << 16)	/* ext refrec */
#define CONFIG_SYS_DDR_TIMING_0	((3 << TIMING_CFG0_RWT_SHIFT) |\
				(3 << TIMING_CFG0_WRT_SHIFT) |\
				(3 << TIMING_CFG0_RRT_SHIFT) |\
				(3 << TIMING_CFG0_WWT_SHIFT) |\
				(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
				(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
				(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
				(2 << TIMING_CFG0_MRS_CYC_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1	((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
				(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
				(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
				(7 << TIMING_CFG1_CASLAT_SHIFT) |\
				(4 << TIMING_CFG1_REFREC_SHIFT) |\
				(4 << TIMING_CFG1_WRREC_SHIFT) |\
				(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
				(2 << TIMING_CFG1_WRTORD_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
				(5 << TIMING_CFG2_CPO_SHIFT) |\
				(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
				(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
				(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
				(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
				(6 << TIMING_CFG2_FOUR_ACT_SHIFT))

#define CONFIG_SYS_DDR_INTERVAL	((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
				(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))

#define CONFIG_SYS_SDRAM_CFG		(SDRAM_CFG_SREN |\
					 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
					 SDRAM_CFG_DBW_32 |\
					 SDRAM_CFG_SDRAM_TYPE_DDR2)

#define CONFIG_SYS_SDRAM_CFG2		0x00401000
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
					 (0x0242 << SDRAM_MODE_SD_SHIFT))
#define CONFIG_SYS_DDR_MODE_2		0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN |\
					 DDRCDR_PZ_NOMZ |\
					 DDRCDR_NZ_NOMZ |\
					 DDRCDR_ODT |\
					 DDRCDR_M_ODR |\
					 DDRCDR_Q_DRN)

/*
 * on-board devices
 */
#define CONFIG_TSEC1
#define CONFIG_TSEC2

/*
 * NOR FLASH setup
 */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_FLASH_SHOW_PROGRESS	50

#define CONFIG_SYS_FLASH_BASE		0xFF800000
#define CONFIG_SYS_FLASH_SIZE		8


#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	128

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/*
 * NAND FLASH setup
 */
#define CONFIG_SYS_NAND_BASE		0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define NAND_CACHE_PAGES		64


/*
 * MRAM setup
 */
#define CONFIG_SYS_MRAM_BASE		0xE2000000
#define CONFIG_SYS_MRAM_SIZE		0x20000	/* 128 Kb */

#define CONFIG_SYS_OR_TIMING_MRAM


/*
 * CPLD setup
 */
#define CONFIG_SYS_CPLD_BASE		0xE3000000
#define CONFIG_SYS_CPLD_SIZE		0x8000

#define CONFIG_SYS_OR_TIMING_MRAM


/*
 * HW-Watchdog
 */
#define CONFIG_WATCHDOG		1
#define CONFIG_SYS_WATCHDOG_VALUE	0xFFFF

/*
 * I2C setup
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR	0x51

/*
 * Ethernet setup
 */
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME		"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define TSEC1_PHY_ADDR			0x1
#define TSEC1_FLAGS			TSEC_GIGABIT
#define TSEC1_PHYIDX			0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME		"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define TSEC2_PHY_ADDR			0x3
#define TSEC2_FLAGS			TSEC_GIGABIT
#define TSEC2_PHYIDX			0
#endif
#define CONFIG_ETHPRIME		"TSEC1"

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM	3

/*
 * U-Boot environment setup
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(8 * 1024 * 1024)

/*
 * Environment Configuration
 */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
				+ CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_NETDEV			eth1
#define CONFIG_HOSTNAME		"ids8313"
#define CONFIG_ROOTPATH		"/opt/eldk-4.2/ppc_6xx"
#define CONFIG_BOOTFILE		"ids8313/uImage"
#define CONFIG_UBOOTPATH		"ids8313/u-boot.bin"
#define CONFIG_FDTFILE			"ids8313/ids8313.dtb"
#define CONFIG_LOADADDR		0x400000
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x00C00000

#define CONFIG_SYS_LOAD_ADDR		0x100000
#define CONFIG_LOADS_ECHO
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTCOMMAND		"run boot_cramfs"
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV		"0"

/* mtdparts command line support */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
	"ethprime=TSEC1\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
	"tftpflash=tftpboot ${loadaddr} ${uboot}; "			\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" +${filesize}; "					\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +${filesize}; "					\
		"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" ${filesize}; "					\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +${filesize}; "					\
		"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" ${filesize}\0"					\
	"console=ttyS0\0"						\
	"fdtaddr=0x780000\0"						\
	"kernel_addr=ff800000\0"					\
	"fdtfile=" __stringify(CONFIG_FDTFILE) "\0"			\
	"setbootargs=setenv bootargs "					\
		"root=${rootdev} rw console=${console},"		\
			"${baudrate} ${othbootargs}\0"			\
	"setipargs=setenv bootargs root=${rootdev} rw "			\
			"nfsroot=${serverip}:${rootpath} "		\
			"ip=${ipaddr}:${serverip}:${gatewayip}:"	\
			"${netmask}:${hostname}:${netdev}:off "		\
			"console=${console},${baudrate} ${othbootargs}\0" \
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
	"\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setipargs;run addmtd;"					\
	"tftp ${loadaddr} ${bootfile};"				\
	"tftp ${fdtaddr} ${fdtfile};"					\
	"fdt addr ${fdtaddr};"						\
	"bootm ${loadaddr} - ${fdtaddr}"

/* UBI Support */

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
eaf8c986 HS	2	/*
	3	* (C) Copyright 2013
	4	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	5	*
	6	* Based on:
	7	* Copyright (c) 2011 IDS GmbH, Germany
	8	* Sergej Stepanov <ste@ids.de>
eaf8c986 HS	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
eaf8c986 HS	17	#define CONFIG_FSL_ELBC
eaf8c986 HS	18
eaf8c986 HS	19	#define CONFIG_BOOT_RETRY_TIME 900
eaf8c986 HS	20	#define CONFIG_BOOT_RETRY_MIN 30
eaf8c986 HS	21	#define CONFIG_RESET_TO_RETRY
eaf8c986 HS	22
eaf8c986 HS	23	#define CONFIG_SYS_SICRH 0x00000000
	24	#define CONFIG_SYS_SICRL (SICRL_LBC \| SICRL_SPI_D)
	25
	26	#define CONFIG_HWCONFIG
	27
eaf8c986 HS	28	/*
	29	* Definitions for initial stack pointer and data area (in DCACHE )
	30	*/
	31	#define CONFIG_SYS_INIT_RAM_LOCK
	32	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
	33	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
	34	#define CONFIG_SYS_GBL_DATA_SIZE 0x100
	35	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
	36	- CONFIG_SYS_GBL_DATA_SIZE)
	37	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	38
eaf8c986 HS	39	/*
	40	* Internal Definitions
	41	*/
	42	/*
	43	* DDR Setup
	44	*/
8a81bfd2	45	#define CONFIG_SYS_SDRAM_BASE 0x00000000
eaf8c986 HS	46
	47	/*
	48	* Manually set up DDR parameters,
	49	* as this board has not the SPD connected to I2C.
	50	*/
	51	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
	52	#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \|\
	53	0x00010000 \|\
	54	CSCONFIG_ROW_BIT_13 \|\
	55	CSCONFIG_COL_BIT_10)
	56
	57	#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG \| \
	58	CSCONFIG_BANK_BIT_3)
	59
	60	#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
	61	#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) \|\
	62	(3 << TIMING_CFG0_WRT_SHIFT) \|\
	63	(3 << TIMING_CFG0_RRT_SHIFT) \|\
	64	(3 << TIMING_CFG0_WWT_SHIFT) \|\
	65	(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \|\
	66	(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \|\
	67	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \| \
	68	(2 << TIMING_CFG0_MRS_CYC_SHIFT))
	69	#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) \|\
	70	(12 << TIMING_CFG1_ACTTOPRE_SHIFT) \|\
	71	(4 << TIMING_CFG1_ACTTORW_SHIFT) \|\
	72	(7 << TIMING_CFG1_CASLAT_SHIFT) \|\
	73	(4 << TIMING_CFG1_REFREC_SHIFT) \|\
	74	(4 << TIMING_CFG1_WRREC_SHIFT) \|\
	75	(2 << TIMING_CFG1_ACTTOACT_SHIFT) \|\
	76	(2 << TIMING_CFG1_WRTORD_SHIFT))
	77	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \|\
	78	(5 << TIMING_CFG2_CPO_SHIFT) \|\
	79	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \|\
	80	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \|\
	81	(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \|\
	82	(1 << TIMING_CFG2_CKE_PLS_SHIFT) \|\
	83	(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
	84
	85	#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) \|\
	86	(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	87
	88	#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \|\
	89	SDRAM_CFG_2T_EN \| SDRAM_CFG_HSE \|\
	90	SDRAM_CFG_DBW_32 \|\
	91	SDRAM_CFG_SDRAM_TYPE_DDR2)
	92
	93	#define CONFIG_SYS_SDRAM_CFG2 0x00401000
	94	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \|\
	95	(0x0242 << SDRAM_MODE_SD_SHIFT))
	96	#define CONFIG_SYS_DDR_MODE_2 0x00000000
	97	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
	98	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \|\
	99	DDRCDR_PZ_NOMZ \|\
	100	DDRCDR_NZ_NOMZ \|\
	101	DDRCDR_ODT \|\
	102	DDRCDR_M_ODR \|\
	103	DDRCDR_Q_DRN)
	104
	105	/*
	106	* on-board devices
	107	*/
	108	#define CONFIG_TSEC1
	109	#define CONFIG_TSEC2
eaf8c986 HS	110
	111	/*
	112	* NOR FLASH setup
	113	*/
eaf8c986 HS	114	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
eaf8c986 HS	115	#define CONFIG_FLASH_SHOW_PROGRESS 50
eaf8c986 HS	116
	117	#define CONFIG_SYS_FLASH_BASE 0xFF800000
	118	#define CONFIG_SYS_FLASH_SIZE 8
eaf8c986	119
a8f97539	120
eaf8c986 HS	121	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	122	#define CONFIG_SYS_MAX_FLASH_SECT 128
	123
	124	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
	125	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	126
	127	/*
	128	* NAND FLASH setup
	129	*/
	130	#define CONFIG_SYS_NAND_BASE 0xE1000000
	131	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	132	#define CONFIG_SYS_NAND_MAX_CHIPS 1
eaf8c986 HS	133	#define CONFIG_NAND_FSL_ELBC
	134	#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
	135	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
	136	#define NAND_CACHE_PAGES 64
	137
eaf8c986 HS	138
	139	/*
	140	* MRAM setup
	141	*/
	142	#define CONFIG_SYS_MRAM_BASE 0xE2000000
	143	#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
eaf8c986 HS	144
	145	#define CONFIG_SYS_OR_TIMING_MRAM
	146
eaf8c986 HS	147
	148	/*
	149	* CPLD setup
	150	*/
	151	#define CONFIG_SYS_CPLD_BASE 0xE3000000
	152	#define CONFIG_SYS_CPLD_SIZE 0x8000
eaf8c986 HS	153
	154	#define CONFIG_SYS_OR_TIMING_MRAM
	155
eaf8c986 HS	156
	157	/*
	158	* HW-Watchdog
	159	*/
	160	#define CONFIG_WATCHDOG 1
	161	#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
	162
	163	/*
	164	* I2C setup
	165	*/
eaf8c986 HS	166	#define CONFIG_SYS_I2C
	167	#define CONFIG_SYS_I2C_FSL
	168	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	169	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	170	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
	171	#define CONFIG_RTC_PCF8563
	172	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	173
eaf8c986 HS	174	/*
	175	* Ethernet setup
	176	*/
	177	#ifdef CONFIG_TSEC1
	178	#define CONFIG_HAS_ETH0
	179	#define CONFIG_TSEC1_NAME "TSEC0"
	180	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	181	#define TSEC1_PHY_ADDR 0x1
	182	#define TSEC1_FLAGS TSEC_GIGABIT
	183	#define TSEC1_PHYIDX 0
	184	#endif
	185
	186	#ifdef CONFIG_TSEC2
	187	#define CONFIG_HAS_ETH1
	188	#define CONFIG_TSEC2_NAME "TSEC1"
	189	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	190	#define TSEC2_PHY_ADDR 0x3
	191	#define TSEC2_FLAGS TSEC_GIGABIT
	192	#define TSEC2_PHYIDX 0
	193	#endif
	194	#define CONFIG_ETHPRIME "TSEC1"
	195
	196	/*
	197	* Serial Port
	198	*/
eaf8c986 HS	199	#define CONFIG_SYS_NS16550_SERIAL
	200	#define CONFIG_SYS_NS16550_REG_SIZE 1
	201
	202	#define CONFIG_SYS_BAUDRATE_TABLE \
	203	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	204	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	205	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
0f06f57c	206	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
eaf8c986 HS	207
	208	#define CONFIG_HAS_FSL_DR_USB
	209	#define CONFIG_SYS_SCCR_USBDRCM 3
	210
eaf8c986 HS	211	/*
	212	* U-Boot environment setup
	213	*/
eaf8c986	214	#define CONFIG_BOOTP_BOOTFILESIZE
eaf8c986 HS	215
	216	/*
	217	* The reserved memory
	218	*/
	219	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	220	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	221	#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
	222
	223	/*
	224	* Environment Configuration
	225	*/
eaf8c986 HS	226	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
	227	+ CONFIG_SYS_MONITOR_LEN)
	228	#define CONFIG_ENV_SIZE 0x20000
	229	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
	230	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	231
eaf8c986	232	#define CONFIG_NETDEV eth1
5bc0543d	233	#define CONFIG_HOSTNAME "ids8313"
eaf8c986 HS	234	#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
	235	#define CONFIG_BOOTFILE "ids8313/uImage"
	236	#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
	237	#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
	238	#define CONFIG_LOADADDR 0x400000
eaf8c986 HS	239	#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
eaf8c986 HS	240
eaf8c986 HS	241	/* Initial Memory map for Linux*/
	242	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
	243
	244	/*
	245	* Miscellaneous configurable options
	246	*/
eaf8c986	247	#define CONFIG_SYS_CBSIZE 1024
eaf8c986	248	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
eaf8c986 HS	249
	250	#define CONFIG_SYS_MEMTEST_START 0x00001000
	251	#define CONFIG_SYS_MEMTEST_END 0x00C00000
	252
	253	#define CONFIG_SYS_LOAD_ADDR 0x100000
eaf8c986 HS	254	#define CONFIG_LOADS_ECHO
eaf8c986 HS	255	#define CONFIG_TIMESTAMP
eaf8c986 HS	256	#define CONFIG_BOOTCOMMAND "run boot_cramfs"
	257	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	258
	259	#define CONFIG_JFFS2_NAND
	260	#define CONFIG_JFFS2_DEV "0"
	261
	262	/* mtdparts command line support */
eaf8c986 HS	263
	264	#define CONFIG_EXTRA_ENV_SETTINGS \
	265	"netdev=" __stringify(CONFIG_NETDEV) "\0" \
	266	"ethprime=TSEC1\0" \
	267	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	268	"tftpflash=tftpboot ${loadaddr} ${uboot}; " \
	269	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	270	" +${filesize}; " \
	271	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	272	" +${filesize}; " \
	273	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
	274	" ${filesize}; " \
	275	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	276	" +${filesize}; " \
	277	"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
	278	" ${filesize}\0" \
	279	"console=ttyS0\0" \
	280	"fdtaddr=0x780000\0" \
	281	"kernel_addr=ff800000\0" \
	282	"fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
	283	"setbootargs=setenv bootargs " \
	284	"root=${rootdev} rw console=${console}," \
	285	"${baudrate} ${othbootargs}\0" \
	286	"setipargs=setenv bootargs root=${rootdev} rw " \
	287	"nfsroot=${serverip}:${rootpath} " \
	288	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	289	"${netmask}:${hostname}:${netdev}:off " \
	290	"console=${console},${baudrate} ${othbootargs}\0" \
	291	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
43ede0bc TR	292	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	293	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
eaf8c986 HS	294	"\0"
	295
	296	#define CONFIG_NFSBOOTCOMMAND \
	297	"setenv rootdev /dev/nfs;" \
	298	"run setipargs;run addmtd;" \
	299	"tftp ${loadaddr} ${bootfile};" \
	300	"tftp ${fdtaddr} ${fdtfile};" \
	301	"fdt addr ${fdtaddr};" \
	302	"bootm ${loadaddr} - ${fdtaddr}"
	303
	304	/* UBI Support */
eaf8c986	305
eaf8c986	306	#endif /* __CONFIG_H */