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1 | /* |
2 | * (C) Copyright 2010 | |
3 | * ISEE 2007 SL, <www.iseebcn.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef __CONFIG_H | |
22 | #define __CONFIG_H | |
23 | #include <asm/sizes.h> | |
24 | ||
25 | /* | |
26 | * High Level Configuration Options | |
27 | */ | |
28 | #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ | |
29 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
30 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
31 | #define CONFIG_OMAP3430 1 /* which is in a 3430 */ | |
32 | #define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */ | |
33 | ||
34 | #define CONFIG_SDRC /* The chip has SDRC controller */ | |
35 | ||
36 | #include <asm/arch/cpu.h> | |
37 | #include <asm/arch/omap3.h> | |
38 | ||
39 | /* | |
40 | * Display CPU and Board information | |
41 | */ | |
42 | #define CONFIG_DISPLAY_CPUINFO 1 | |
43 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
44 | ||
45 | /* Clock Defines */ | |
46 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
47 | #define V_SCLK (V_OSCK >> 1) | |
48 | ||
49 | #define CONFIG_MISC_INIT_R | |
50 | ||
51 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
52 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
53 | #define CONFIG_INITRD_TAG 1 | |
54 | #define CONFIG_REVISION_TAG 1 | |
55 | ||
56 | /* | |
57 | * NS16550 Configuration | |
58 | */ | |
59 | ||
60 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
61 | ||
62 | #define CONFIG_SYS_NS16550 | |
63 | #define CONFIG_SYS_NS16550_SERIAL | |
64 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
65 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
66 | ||
67 | /* select serial console configuration */ | |
68 | #define CONFIG_CONS_INDEX 3 | |
69 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
70 | #define CONFIG_SERIAL3 3 | |
71 | ||
72 | /* allow to overwrite serial and ethaddr */ | |
73 | #define CONFIG_ENV_OVERWRITE | |
74 | #define CONFIG_BAUDRATE 115200 | |
75 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} | |
76 | #define CONFIG_MMC 1 | |
77 | #define CONFIG_OMAP3_MMC 1 | |
78 | #define CONFIG_DOS_PARTITION 1 | |
79 | ||
80 | /* DDR */ | |
81 | #define CONFIG_OMAP3_NUMONYX_DDR 1 | |
82 | ||
83 | /* USB */ | |
84 | #define CONFIG_MUSB_UDC 1 | |
85 | #define CONFIG_USB_OMAP3 1 | |
86 | #define CONFIG_TWL4030_USB 1 | |
87 | ||
88 | /* USB device configuration */ | |
89 | #define CONFIG_USB_DEVICE 1 | |
90 | #define CONFIG_USB_TTY 1 | |
91 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
92 | ||
93 | /* Change these to suit your needs */ | |
94 | #define CONFIG_USBD_VENDORID 0x0451 | |
95 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
96 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
97 | #define CONFIG_USBD_PRODUCT_NAME "IGEP" | |
98 | ||
99 | /* commands to include */ | |
100 | #include <config_cmd_default.h> | |
101 | ||
102 | #define CONFIG_CMD_CACHE | |
103 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
104 | #define CONFIG_CMD_FAT /* FAT support */ | |
105 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
106 | #define CONFIG_CMD_MMC /* MMC support */ | |
107 | #define CONFIG_CMD_ONENAND /* ONENAND support */ | |
108 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
109 | #define CONFIG_CMD_DHCP | |
110 | #define CONFIG_CMD_PING | |
111 | #define CONFIG_CMD_NFS /* NFS support */ | |
112 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ | |
113 | #define CONFIG_MTD_DEVICE | |
114 | ||
115 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
116 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
117 | ||
118 | #define CONFIG_SYS_NO_FLASH | |
119 | #define CONFIG_HARD_I2C 1 | |
120 | #define CONFIG_SYS_I2C_SPEED 100000 | |
121 | #define CONFIG_SYS_I2C_SLAVE 1 | |
122 | #define CONFIG_SYS_I2C_BUS 0 | |
123 | #define CONFIG_SYS_I2C_BUS_SELECT 1 | |
124 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 | |
125 | ||
126 | /* | |
127 | * TWL4030 | |
128 | */ | |
129 | #define CONFIG_TWL4030_POWER 1 | |
130 | ||
131 | /* Environment information */ | |
132 | #define CONFIG_BOOTCOMMAND \ | |
133 | "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" | |
134 | ||
135 | #define CONFIG_BOOTDELAY 3 | |
136 | ||
137 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
138 | "usbtty=cdc_acm\0" | |
139 | ||
140 | #define CONFIG_AUTO_COMPLETE 1 | |
141 | ||
142 | /* | |
143 | * Miscellaneous configurable options | |
144 | */ | |
145 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
146 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
147 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
148 | #define CONFIG_SYS_PROMPT "U-Boot # " | |
149 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
150 | /* Print Buffer Size */ | |
151 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
152 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
153 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
154 | /* Boot Argument Buffer Size */ | |
155 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
156 | ||
157 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
158 | /* works on */ | |
159 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
160 | 0x01F00000) /* 31MB */ | |
161 | ||
162 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
163 | /* load address */ | |
164 | ||
165 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
166 | ||
167 | /* | |
168 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
169 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
170 | * This rate is divided by a local divisor. | |
171 | */ | |
172 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
173 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
174 | #define CONFIG_SYS_HZ 1000 | |
175 | ||
176 | /* | |
177 | * Stack sizes | |
178 | * | |
179 | * The stack sizes are set up in start.S using the settings below | |
180 | */ | |
181 | #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ | |
182 | ||
183 | /* | |
184 | * Physical Memory Map | |
185 | * | |
186 | */ | |
187 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
188 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
189 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ | |
190 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
191 | ||
192 | /* SDRAM Bank Allocation method */ | |
193 | #define SDRC_R_B_C 1 | |
194 | ||
195 | /* | |
196 | * FLASH and environment organization | |
197 | */ | |
198 | ||
199 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ | |
200 | ||
201 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
202 | ||
203 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
204 | ||
205 | #define CONFIG_ENV_IS_IN_ONENAND 1 | |
206 | #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ | |
207 | #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET | |
208 | ||
209 | /* | |
210 | * Size of malloc() pool | |
211 | */ | |
212 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
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213 | |
214 | /* | |
215 | * SMSC911x Ethernet | |
216 | */ | |
217 | #if defined(CONFIG_CMD_NET) | |
218 | #define CONFIG_NET_MULTI | |
219 | #define CONFIG_SMC911X | |
220 | #define CONFIG_SMC911X_32_BIT | |
221 | #define CONFIG_SMC911X_BASE 0x2C000000 | |
222 | #endif /* (CONFIG_CMD_NET) */ | |
223 | ||
224 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
31bfcf1c SS |
225 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
226 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
227 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
228 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
229 | GENERATED_GBL_DATA_SIZE) | |
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230 | |
231 | #endif /* __CONFIG_H */ |