[thirdparty/u-boot.git] / include / configs / impa7.h

/*
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the implementa impA7 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
#define CONFIG_IMPA7		1	/* on an impA7 Board      */
#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
#define CONFIG_ARM7_REVD	1 	/* enable ARM720 REV.D Workarounds */

#undef CONFIG_USE_IRQ			/* don't need them anymore */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
#define CS8900_BASE		0x20000000
#define CS8900_BUS32		1

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1		1	/* we use Serial line 1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		9600

#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
/*#define CONFIG_ETHADDR	08:00:3e:26:0a:5a	*/
/*#define CONFIG_NETMASK        255.255.0.0	*/
/*#define CONFIG_IPADDR		172.22.2.128	*/
/*#define CONFIG_SERVERIP	172.22.2.126	*/
/*#define CONFIG_BOOTFILE	"impa7"	*/
#define CONFIG_BOOTCOMMAND	"bootp;bootm"

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		"impA7 # "		/* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/

#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define	CFG_LOAD_ADDR		0xc1000000	/* default load address	*/

#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */

						/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x10000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x00800000 /* 16 MB */

#define CFG_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Flash banks JFFS2 should use */
#define CFG_JFFS2_FIRST_BANK    0
#define CFG_JFFS2_FIRST_SECTOR	8
#define CFG_JFFS2_NUM_BANKS     2

#endif	/* __CONFIG_H */
Commit	Line	Data
da27dcf0 WD	1	/*
	2	* (C) Copyright 2000
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* Configuation settings for the implementa impA7 board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
da27dcf0 WD	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34	#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
	35	#define CONFIG_IMPA7 1 /* on an impA7 Board */
	36	#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
	37	#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */
	38
	39	#undef CONFIG_USE_IRQ /* don't need them anymore */
	40
	41	/*
	42	* Size of malloc() pool
	43	*/
699b13a6	44	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
a8c7c708	45	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
da27dcf0 WD	46
	47	/*
	48	* Hardware drivers
	49	*/
	50	#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
	51	#define CS8900_BASE 0x20000000
	52	#define CS8900_BUS32 1
	53
	54	/*
	55	* select serial console configuration
	56	*/
	57	#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
	58
	59	/* allow to overwrite serial and ethaddr */
	60	#define CONFIG_ENV_OVERWRITE
	61
	62	#define CONFIG_BAUDRATE 9600
	63
	64	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT\|CONFIG_BOOTP_BOOTFILESIZE)
	65
	66	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| CFG_CMD_JFFS2)
	67
	68	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	69	#include <cmd_confdefs.h>
	70
	71	#define CONFIG_BOOTDELAY 3
	72	#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
	73	/#define CONFIG_ETHADDR 08:00:3e:26:0a:5a /
	74	/#define CONFIG_NETMASK 255.255.0.0 /
	75	/#define CONFIG_IPADDR 172.22.2.128 /
	76	/#define CONFIG_SERVERIP 172.22.2.126 /
	77	/#define CONFIG_BOOTFILE "impa7" /
	78	#define CONFIG_BOOTCOMMAND "bootp;bootm"
	79
	80	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	81	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	82	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	83	#endif
	84
	85	/*
	86	* Miscellaneous configurable options
	87	*/
	88	#define CFG_LONGHELP /* undef to save memory */
	89	#define CFG_PROMPT "impA7 # " /* Monitor Command Prompt */
	90	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	91	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	92	#define CFG_MAXARGS 16 /* max number of command args */
	93	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	94
	95	#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
	96	#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
	97
	98	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	99
	100	#define CFG_LOAD_ADDR 0xc1000000 /* default load address */
	101
	102	#define CFG_HZ 2000 /* decrementer freq: 2 kHz */
	103
	104	/* valid baudrates */
	105	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	106
	107	/*-----------------------------------------------------------------------
	108	* Stack sizes
	109	*
110	* The stack sizes are set up in start.S using the settings below
111	*/
112	#define CONFIG_STACKSIZE (1281024) / regular stack */
113	#ifdef CONFIG_USE_IRQ
114	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
115	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
116	#endif
117
118	/*-----------------------------------------------------------------------
119	* Physical Memory Map
120	*/
121	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
122	#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
123	#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
124	#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */
125	#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
126
127	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
128	#define PHYS_FLASH_2 0x10000000 /* Flash Bank #2 */
129	#define PHYS_FLASH_SIZE 0x00800000 /* 16 MB */
130
131	#define CFG_FLASH_BASE PHYS_FLASH_1
132
133	/*-----------------------------------------------------------------------
134	* FLASH and environment organization
135	*/
136	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
137	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
138
139	/* timeout values are in ticks */
140	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
141	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
142
143	#define CFG_ENV_IS_IN_FLASH 1
144	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
145	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
146
147	/* Flash banks JFFS2 should use */
148	#define CFG_JFFS2_FIRST_BANK 0
149	#define CFG_JFFS2_FIRST_SECTOR 8
150	#define CFG_JFFS2_NUM_BANKS 2
151
152	#endif /* __CONFIG_H */