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Commit | Line | Data |
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caebc95b SH |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Kshitij Gupta <kshitij@ti.com> | |
6 | * | |
7064122c | 7 | * Configuration settings for the LogicPD i.MX31 Litekit board. |
caebc95b | 8 | * |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
caebc95b SH |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
86271115 | 15 | #include <asm/arch/imx-regs.h> |
e7ae84d6 | 16 | |
caebc95b | 17 | /* High Level Configuration Options */ |
3fd968e9 | 18 | #define CONFIG_MX31 1 /* This is a mx31 */ |
caebc95b SH |
19 | #define CONFIG_MX31_CLK32 32000 |
20 | ||
21 | #define CONFIG_DISPLAY_CPUINFO | |
22 | #define CONFIG_DISPLAY_BOARDINFO | |
23 | ||
ac88e66e FE |
24 | #define CONFIG_SYS_TEXT_BASE 0xa0000000 |
25 | ||
4c414387 FE |
26 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE |
27 | ||
caebc95b SH |
28 | /* Temporarily disabled */ |
29 | #if 0 | |
30 | #define CONFIG_OF_LIBFDT 1 | |
31 | #define CONFIG_FIT 1 | |
32 | #define CONFIG_FIT_VERBOSE 1 | |
33 | #endif | |
34 | ||
35 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
36 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
37 | #define CONFIG_INITRD_TAG 1 | |
38 | ||
39 | /* | |
40 | * Size of malloc() pool | |
41 | */ | |
6d0f6bcf | 42 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
caebc95b SH |
43 | |
44 | /* | |
45 | * Hardware drivers | |
46 | */ | |
47 | ||
40f6fffe SB |
48 | #define CONFIG_MXC_UART |
49 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
87e14f0f | 50 | #define CONFIG_MXC_GPIO |
caebc95b | 51 | |
f9204e15 ML |
52 | #define CONFIG_HARD_SPI 1 |
53 | #define CONFIG_MXC_SPI 1 | |
d255bb0e | 54 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 55 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
f9204e15 | 56 | |
2672d5db | 57 | /* PMIC Controller */ |
be3b51aa ŁM |
58 | #define CONFIG_POWER |
59 | #define CONFIG_POWER_SPI | |
60 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
61 | #define CONFIG_FSL_PMIC_BUS 1 |
62 | #define CONFIG_FSL_PMIC_CS 0 | |
63 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 64 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
2672d5db | 65 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 66 | #define CONFIG_RTC_MC13XXX |
f9204e15 | 67 | |
caebc95b SH |
68 | /* allow to overwrite serial and ethaddr */ |
69 | #define CONFIG_ENV_OVERWRITE | |
70 | #define CONFIG_CONS_INDEX 1 | |
71 | #define CONFIG_BAUDRATE 115200 | |
caebc95b SH |
72 | |
73 | /*********************************************************** | |
74 | * Command definition | |
75 | ***********************************************************/ | |
caebc95b SH |
76 | #define CONFIG_CMD_MII |
77 | #define CONFIG_CMD_PING | |
f9204e15 ML |
78 | #define CONFIG_CMD_SPI |
79 | #define CONFIG_CMD_DATE | |
ba6adeb4 | 80 | #define CONFIG_CMD_NAND |
caebc95b SH |
81 | |
82 | #define CONFIG_BOOTDELAY 3 | |
83 | ||
84 | #define CONFIG_NETMASK 255.255.255.0 | |
85 | #define CONFIG_IPADDR 192.168.23.168 | |
86 | #define CONFIG_SERVERIP 192.168.23.2 | |
87 | ||
88 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
89 | "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ | |
90 | "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ | |
91 | "bootcmd=run bootcmd_net\0" \ | |
92 | "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ | |
93 | "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" | |
94 | ||
95 | ||
736fead8 BW |
96 | #define CONFIG_SMC911X 1 |
97 | #define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000) | |
98 | #define CONFIG_SMC911X_32_BIT 1 | |
caebc95b SH |
99 | |
100 | /* | |
101 | * Miscellaneous configurable options | |
102 | */ | |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
104 | #define CONFIG_SYS_PROMPT "uboot> " | |
105 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
caebc95b | 106 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
108 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
109 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
caebc95b | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
112 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
caebc95b | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ |
caebc95b | 115 | |
caebc95b SH |
116 | #define CONFIG_CMDLINE_EDITING 1 |
117 | ||
caebc95b SH |
118 | /*----------------------------------------------------------------------- |
119 | * Physical Memory Map | |
120 | */ | |
121 | #define CONFIG_NR_DRAM_BANKS 1 | |
e7ae84d6 | 122 | #define PHYS_SDRAM_1 CSD0_BASE |
caebc95b | 123 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) |
4e37731a | 124 | #define CONFIG_BOARD_EARLY_INIT_F |
caebc95b | 125 | |
7a5faf08 | 126 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
68a75d0b | 127 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
553f0982 | 128 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
25ddd1fb | 129 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
68a75d0b ML |
130 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) |
131 | ||
caebc95b SH |
132 | /*----------------------------------------------------------------------- |
133 | * FLASH and environment organization | |
134 | */ | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_FLASH_BASE CS0_BASE |
136 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
137 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
138 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
caebc95b | 139 | |
6d0f6bcf | 140 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000) |
5a1aceb0 | 141 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
142 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
143 | #define CONFIG_ENV_SIZE (64 * 1024) | |
caebc95b SH |
144 | |
145 | /*----------------------------------------------------------------------- | |
146 | * CFI FLASH driver setup | |
147 | */ | |
6d0f6bcf | 148 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
00b1883a | 149 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
151 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
caebc95b SH |
152 | |
153 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
155 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
caebc95b SH |
156 | |
157 | /* | |
158 | * JFFS2 partitions | |
159 | */ | |
68d7d651 | 160 | #undef CONFIG_CMD_MTDPARTS |
caebc95b SH |
161 | #define CONFIG_JFFS2_DEV "nor0" |
162 | ||
ba6adeb4 ML |
163 | /* |
164 | * NAND flash | |
165 | */ | |
166 | #define CONFIG_NAND_MXC | |
167 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR | |
168 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
169 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
170 | #define CONFIG_MXC_NAND_HWECC | |
171 | ||
caebc95b | 172 | #endif /* __CONFIG_H */ |