]>
Commit | Line | Data |
---|---|---|
86ac7a9a PF |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright 2018 NXP | |
4 | */ | |
5 | ||
6 | #ifndef __IMX8M_EVK_H | |
7 | #define __IMX8M_EVK_H | |
8 | ||
9 | #include <linux/sizes.h> | |
1af3c7f4 | 10 | #include <linux/stringify.h> |
86ac7a9a PF |
11 | #include <asm/arch/imx-regs.h> |
12 | ||
13586e46 | 13 | #define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) |
b297c0d7 | 14 | |
86ac7a9a | 15 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
86ac7a9a PF |
16 | |
17 | #ifdef CONFIG_SPL_BUILD | |
18 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ | |
86ac7a9a | 19 | #define CONFIG_SPL_STACK 0x187FF0 |
86ac7a9a PF |
20 | #define CONFIG_SPL_BSS_START_ADDR 0x00180000 |
21 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ | |
22 | #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 | |
23 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ | |
24 | #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 | |
86ac7a9a PF |
25 | |
26 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ | |
27 | #define CONFIG_MALLOC_F_ADDR 0x182000 | |
28 | /* For RAW image gives a error info not panic */ | |
29 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE | |
30 | ||
86ac7a9a PF |
31 | #define CONFIG_POWER_PFUZE100 |
32 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
33 | #endif | |
34 | ||
86ac7a9a PF |
35 | /* ENET Config */ |
36 | /* ENET1 */ | |
37 | #if defined(CONFIG_CMD_NET) | |
86ac7a9a | 38 | #define CONFIG_FEC_MXC_PHYADDR 0 |
86ac7a9a PF |
39 | #endif |
40 | ||
5b3c76e8 AG |
41 | #ifndef CONFIG_SPL_BUILD |
42 | #define BOOT_TARGET_DEVICES(func) \ | |
43 | func(MMC, mmc, 0) \ | |
44 | func(MMC, mmc, 1) \ | |
45 | func(DHCP, dhcp, na) | |
46 | ||
47 | #include <config_distro_bootcmd.h> | |
48 | #endif | |
49 | ||
86ac7a9a PF |
50 | /* Initial environment variables */ |
51 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5b3c76e8 | 52 | BOOTENV \ |
efaf9a2b AZ |
53 | "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
54 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
86ac7a9a | 55 | "image=Image\0" \ |
502f3ca0 | 56 | "console=ttymxc0,115200\0" \ |
efaf9a2b | 57 | "fdt_addr_r=0x43000000\0" \ |
86ac7a9a | 58 | "boot_fdt=try\0" \ |
efaf9a2b | 59 | "fdtfile=imx8mq-evk.dtb\0" \ |
86ac7a9a | 60 | "initrd_addr=0x43800000\0" \ |
acbc1d86 | 61 | "bootm_size=0x10000000\0" \ |
de35b8f9 | 62 | "mmcpart=1\0" \ |
adfaa428 | 63 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
86ac7a9a PF |
64 | |
65 | /* Link Definitions */ | |
86ac7a9a PF |
66 | |
67 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
68 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | |
69 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
70 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
71 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
72 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
73 | ||
86ac7a9a | 74 | |
86ac7a9a PF |
75 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
76 | #define PHYS_SDRAM 0x40000000 | |
77 | #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ | |
78 | ||
52b6b480 | 79 | #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) |
86ac7a9a | 80 | |
86ac7a9a PF |
81 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
82 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
83 | ||
86ac7a9a | 84 | #endif |