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Commit | Line | Data |
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138ff60c | 1 | /* |
e979e85f DZ |
2 | * (C) Copyright 2009 |
3 | * Detlev Zundel, DENX Software Engineering, dzu@denx.de. | |
4 | * | |
414eec35 | 5 | * (C) Copyright 2003-2005 |
138ff60c WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
138ff60c WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 MY |
19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
20 | #define CONFIG_INKA4X0 1 /* INKA4x0 board */ | |
138ff60c | 21 | |
2ae18241 WD |
22 | /* |
23 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
24 | * 0xFFE00000 boot low | |
25 | * 0x00100000 boot from RAM (for testing only) | |
26 | */ | |
27 | #ifndef CONFIG_SYS_TEXT_BASE | |
28 | #define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ | |
29 | #endif | |
2ced53e1 | 30 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" |
2ae18241 | 31 | |
6d0f6bcf | 32 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
138ff60c | 33 | |
151ab83a WD |
34 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
35 | ||
31d82672 BB |
36 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
37 | ||
138ff60c WD |
38 | /* |
39 | * Serial console configuration | |
40 | */ | |
151ab83a | 41 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
6d0f6bcf | 42 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
138ff60c | 43 | |
436be29c WD |
44 | /* |
45 | * PCI Mapping: | |
46 | * 0x40000000 - 0x4fffffff - PCI Memory | |
47 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
48 | */ | |
436be29c | 49 | #define CONFIG_PCI_SCAN_SHOW 1 |
f33fca22 | 50 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
436be29c WD |
51 | |
52 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
53 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
54 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
55 | ||
56 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
57 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
58 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
59 | ||
6d0f6bcf | 60 | #define CONFIG_SYS_XLB_PIPELINING 1 |
436be29c WD |
61 | |
62 | /* Partitions */ | |
436be29c | 63 | |
7f5c0157 JL |
64 | /* |
65 | * BOOTP options | |
66 | */ | |
67 | #define CONFIG_BOOTP_BOOTFILESIZE | |
68 | #define CONFIG_BOOTP_BOOTPATH | |
69 | #define CONFIG_BOOTP_GATEWAY | |
70 | #define CONFIG_BOOTP_HOSTNAME | |
71 | ||
138ff60c | 72 | /* |
1d2c6bc4 | 73 | * Command line configuration. |
138ff60c | 74 | */ |
1d2c6bc4 | 75 | #define CONFIG_CMD_PCI |
1d2c6bc4 | 76 | |
b05dcb58 WD |
77 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
78 | ||
14d0a02a | 79 | #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ |
6d0f6bcf | 80 | # define CONFIG_SYS_LOWBOOT 1 |
138ff60c WD |
81 | #endif |
82 | ||
83 | /* | |
84 | * Autobooting | |
85 | */ | |
138ff60c WD |
86 | |
87 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 88 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
138ff60c WD |
89 | "echo" |
90 | ||
91 | #undef CONFIG_BOOTARGS | |
92 | ||
84e106c0 WD |
93 | #define CONFIG_IPADDR 192.168.100.2 |
94 | #define CONFIG_SERVERIP 192.168.100.1 | |
95 | #define CONFIG_NETMASK 255.255.255.0 | |
96 | #define HOSTNAME inka4x0 | |
b3f44c21 | 97 | #define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage" |
8b3637c6 | 98 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
84e106c0 | 99 | |
138ff60c WD |
100 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
101 | "netdev=eth0\0" \ | |
102 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 103 | "nfsroot=${serverip}:${rootpath}\0" \ |
138ff60c | 104 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
105 | "addip=setenv bootargs ${bootargs} " \ |
106 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
107 | ":${hostname}:${netdev}:off panic=1\0" \ | |
84e106c0 WD |
108 | "addcons=setenv bootargs ${bootargs} " \ |
109 | "console=ttyS0,${baudrate}\0" \ | |
110 | "flash_nfs=run nfsargs addip addcons;" \ | |
fe126d8b | 111 | "bootm ${kernel_addr}\0" \ |
84e106c0 WD |
112 | "net_nfs=tftp 200000 ${bootfile};" \ |
113 | "run nfsargs addip addcons;bootm\0" \ | |
114 | "enable_disp=mw.l 100000 04000000 1;" \ | |
115 | "cp.l 100000 f0000b20 1;" \ | |
116 | "cp.l 100000 f0000b28 1\0" \ | |
117 | "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ | |
118 | "ide_boot=ext2load ide 0:1 200000 uImage;" \ | |
f23cb34c | 119 | "run ideargs addip addcons enable_disp;bootm\0" \ |
84e106c0 | 120 | "brightness=255\0" \ |
138ff60c WD |
121 | "" |
122 | ||
84e106c0 | 123 | #define CONFIG_BOOTCOMMAND "run ide_boot" |
138ff60c WD |
124 | |
125 | /* | |
126 | * IPB Bus clocking configuration. | |
127 | */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
138ff60c WD |
129 | |
130 | /* | |
131 | * Flash configuration | |
132 | */ | |
6d0f6bcf | 133 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 134 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
136 | #define CONFIG_SYS_FLASH_SIZE 0x00200000 | |
137 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
138 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
139 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
140 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
138ff60c WD |
141 | |
142 | /* | |
143 | * Environment settings | |
144 | */ | |
5a1aceb0 | 145 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 146 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 JCPV |
147 | #define CONFIG_ENV_SIZE 0x2000 |
148 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
138ff60c | 149 | #define CONFIG_ENV_OVERWRITE 1 |
6d0f6bcf | 150 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
138ff60c WD |
151 | |
152 | /* | |
153 | * Memory map | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MBAR 0xF0000000 |
156 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
157 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
138ff60c | 158 | |
5fb6d719 MB |
159 | /* |
160 | * SDRAM controller configuration | |
161 | */ | |
162 | #undef CONFIG_SDR_MT48LC16M16A2 | |
163 | #undef CONFIG_DDR_MT46V16M16 | |
164 | #undef CONFIG_DDR_MT46V32M16 | |
165 | #undef CONFIG_DDR_HYB25D512160BF | |
166 | #define CONFIG_DDR_K4H511638C | |
138ff60c WD |
167 | |
168 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
800eb096 | 170 | |
138ff60c | 171 | /* preserve space for the post_word at end of on-chip SRAM */ |
800eb096 MZ |
172 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
173 | ||
174 | #ifdef CONFIG_POST | |
553f0982 | 175 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
138ff60c | 176 | #else |
553f0982 | 177 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
138ff60c WD |
178 | #endif |
179 | ||
25ddd1fb | 180 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 181 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
138ff60c | 182 | |
14d0a02a | 183 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
184 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
185 | # define CONFIG_SYS_RAMBOOT 1 | |
138ff60c WD |
186 | #endif |
187 | ||
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
189 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
190 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
138ff60c WD |
191 | |
192 | /* | |
193 | * Ethernet configuration | |
194 | */ | |
195 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 196 | #define CONFIG_MPC5xxx_FEC_MII100 |
138ff60c | 197 | /* |
86321fc1 | 198 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
138ff60c | 199 | */ |
86321fc1 | 200 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
138ff60c | 201 | #define CONFIG_PHY_ADDR 0x00 |
84e106c0 | 202 | #define CONFIG_MII |
138ff60c WD |
203 | |
204 | /* | |
205 | * GPIO configuration | |
206 | * | |
9f709b6c WD |
207 | * use CS1 as gpio_wkup_6 output |
208 | * Bit 0 (mask: 0x80000000): 0 | |
138ff60c WD |
209 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
210 | * 00 -> No Alternatives, I2C1 is used for onboard EEPROM | |
211 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard | |
212 | * EEPROM | |
213 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
e979e85f DZ |
214 | * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 |
215 | * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 | |
216 | * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 | |
138ff60c | 217 | */ |
e979e85f | 218 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 |
138ff60c | 219 | |
138ff60c WD |
220 | /* |
221 | * Miscellaneous configurable options | |
222 | */ | |
6d0f6bcf | 223 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1d2c6bc4 | 224 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 225 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
138ff60c | 226 | #else |
6d0f6bcf | 227 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
138ff60c | 228 | #endif |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
230 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
231 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
138ff60c | 232 | |
6d0f6bcf | 233 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
1d2c6bc4 | 234 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 235 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
1d2c6bc4 JL |
236 | #endif |
237 | ||
138ff60c | 238 | /* Enable an alternate, more extensive memory test */ |
6d0f6bcf | 239 | #define CONFIG_SYS_ALT_MEMTEST |
138ff60c | 240 | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
242 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
138ff60c | 243 | |
6d0f6bcf | 244 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
138ff60c | 245 | |
138ff60c WD |
246 | /* |
247 | * Various low-level settings | |
248 | */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
250 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
138ff60c | 251 | |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
253 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
254 | #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ | |
255 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
256 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
138ff60c | 257 | |
e58cf2a0 | 258 | /* 32Mbit SRAM @0x30000000 */ |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_CS1_START 0x30000000 |
260 | #define CONFIG_SYS_CS1_SIZE 0x00400000 | |
261 | #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 WD |
262 | |
263 | /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_CS2_START 0x80000000 |
265 | #define CONFIG_SYS_CS2_SIZE 0x0001000 | |
266 | #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 | 267 | |
f4733a07 | 268 | /* GPIO in @0x30400000 */ |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_CS3_START 0x30400000 |
270 | #define CONFIG_SYS_CS3_SIZE 0x00100000 | |
271 | #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
f4733a07 | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_CS_BURST 0x00000000 |
274 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
138ff60c | 275 | |
436be29c WD |
276 | /*----------------------------------------------------------------------- |
277 | * USB stuff | |
278 | *----------------------------------------------------------------------- | |
279 | */ | |
280 | #define CONFIG_USB_OHCI | |
151ab83a WD |
281 | #define CONFIG_USB_CLOCK 0x00015555 |
282 | #define CONFIG_USB_CONFIG 0x00001000 | |
436be29c | 283 | |
b05dcb58 WD |
284 | /*----------------------------------------------------------------------- |
285 | * IDE/ATA stuff Supports IDE harddisk | |
286 | *----------------------------------------------------------------------- | |
287 | */ | |
288 | ||
289 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
290 | ||
291 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
292 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
293 | ||
b05dcb58 WD |
294 | #define CONFIG_IDE_PREINIT |
295 | ||
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
297 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
b05dcb58 | 298 | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
300 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
301 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ | |
302 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ | |
303 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ | |
304 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
b05dcb58 WD |
305 | |
306 | #define CONFIG_ATAPI 1 | |
1806c759 | 307 | |
6d0f6bcf | 308 | #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ |
b05dcb58 | 309 | |
138ff60c | 310 | #endif /* __CONFIG_H */ |