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138ff60c | 1 | /* |
e979e85f DZ |
2 | * (C) Copyright 2009 |
3 | * Detlev Zundel, DENX Software Engineering, dzu@denx.de. | |
4 | * | |
414eec35 | 5 | * (C) Copyright 2003-2005 |
138ff60c WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
151ab83a WD |
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_INKA4X0 1 /* INKA4x0 board */ | |
138ff60c | 38 | |
2ae18241 WD |
39 | /* |
40 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
41 | * 0xFFE00000 boot low | |
42 | * 0x00100000 boot from RAM (for testing only) | |
43 | */ | |
44 | #ifndef CONFIG_SYS_TEXT_BASE | |
45 | #define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ | |
46 | #endif | |
47 | ||
6d0f6bcf | 48 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
138ff60c | 49 | |
151ab83a WD |
50 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
51 | ||
31d82672 BB |
52 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
53 | ||
138ff60c WD |
54 | /* |
55 | * Serial console configuration | |
56 | */ | |
151ab83a WD |
57 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
58 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 59 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
138ff60c | 60 | |
436be29c WD |
61 | /* |
62 | * PCI Mapping: | |
63 | * 0x40000000 - 0x4fffffff - PCI Memory | |
64 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
65 | */ | |
66 | #define CONFIG_PCI 1 | |
67 | #define CONFIG_PCI_PNP 1 | |
68 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 69 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
436be29c WD |
70 | |
71 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
72 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
73 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
74 | ||
75 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
76 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
77 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
78 | ||
6d0f6bcf | 79 | #define CONFIG_SYS_XLB_PIPELINING 1 |
436be29c WD |
80 | |
81 | /* Partitions */ | |
82 | #define CONFIG_MAC_PARTITION | |
83 | #define CONFIG_DOS_PARTITION | |
84 | #define CONFIG_ISO_PARTITION | |
85 | ||
1d2c6bc4 | 86 | |
7f5c0157 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_BOOTFILESIZE | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
92 | #define CONFIG_BOOTP_GATEWAY | |
93 | #define CONFIG_BOOTP_HOSTNAME | |
94 | ||
95 | ||
138ff60c | 96 | /* |
1d2c6bc4 | 97 | * Command line configuration. |
138ff60c | 98 | */ |
1d2c6bc4 JL |
99 | #include <config_cmd_default.h> |
100 | ||
e979e85f | 101 | #define CONFIG_CMD_DATE |
1d2c6bc4 JL |
102 | #define CONFIG_CMD_DHCP |
103 | #define CONFIG_CMD_EXT2 | |
104 | #define CONFIG_CMD_FAT | |
105 | #define CONFIG_CMD_IDE | |
106 | #define CONFIG_CMD_NFS | |
107 | #define CONFIG_CMD_PCI | |
e979e85f | 108 | #define CONFIG_CMD_PING |
1d2c6bc4 JL |
109 | #define CONFIG_CMD_SNTP |
110 | #define CONFIG_CMD_USB | |
111 | ||
b05dcb58 WD |
112 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
113 | ||
14d0a02a | 114 | #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ |
6d0f6bcf | 115 | # define CONFIG_SYS_LOWBOOT 1 |
138ff60c WD |
116 | #endif |
117 | ||
118 | /* | |
119 | * Autobooting | |
120 | */ | |
84e106c0 | 121 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
138ff60c WD |
122 | |
123 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 124 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
138ff60c WD |
125 | "echo" |
126 | ||
127 | #undef CONFIG_BOOTARGS | |
128 | ||
84e106c0 WD |
129 | #define CONFIG_ETHADDR 00:a0:a4:03:00:00 |
130 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
131 | ||
132 | #define CONFIG_IPADDR 192.168.100.2 | |
133 | #define CONFIG_SERVERIP 192.168.100.1 | |
134 | #define CONFIG_NETMASK 255.255.255.0 | |
135 | #define HOSTNAME inka4x0 | |
136 | #define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage | |
137 | #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx | |
138 | ||
138ff60c WD |
139 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
140 | "netdev=eth0\0" \ | |
141 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 142 | "nfsroot=${serverip}:${rootpath}\0" \ |
138ff60c | 143 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
144 | "addip=setenv bootargs ${bootargs} " \ |
145 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
146 | ":${hostname}:${netdev}:off panic=1\0" \ | |
84e106c0 WD |
147 | "addcons=setenv bootargs ${bootargs} " \ |
148 | "console=ttyS0,${baudrate}\0" \ | |
149 | "flash_nfs=run nfsargs addip addcons;" \ | |
fe126d8b | 150 | "bootm ${kernel_addr}\0" \ |
84e106c0 WD |
151 | "net_nfs=tftp 200000 ${bootfile};" \ |
152 | "run nfsargs addip addcons;bootm\0" \ | |
153 | "enable_disp=mw.l 100000 04000000 1;" \ | |
154 | "cp.l 100000 f0000b20 1;" \ | |
155 | "cp.l 100000 f0000b28 1\0" \ | |
156 | "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ | |
157 | "ide_boot=ext2load ide 0:1 200000 uImage;" \ | |
f23cb34c | 158 | "run ideargs addip addcons enable_disp;bootm\0" \ |
84e106c0 | 159 | "brightness=255\0" \ |
138ff60c WD |
160 | "" |
161 | ||
84e106c0 | 162 | #define CONFIG_BOOTCOMMAND "run ide_boot" |
138ff60c WD |
163 | |
164 | /* | |
165 | * IPB Bus clocking configuration. | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
138ff60c WD |
168 | |
169 | /* | |
170 | * Flash configuration | |
171 | */ | |
6d0f6bcf | 172 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 173 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
175 | #define CONFIG_SYS_FLASH_SIZE 0x00200000 | |
176 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
177 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
178 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
179 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
138ff60c WD |
180 | |
181 | /* | |
182 | * Environment settings | |
183 | */ | |
5a1aceb0 | 184 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 185 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 JCPV |
186 | #define CONFIG_ENV_SIZE 0x2000 |
187 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
138ff60c | 188 | #define CONFIG_ENV_OVERWRITE 1 |
6d0f6bcf | 189 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
138ff60c WD |
190 | |
191 | /* | |
192 | * Memory map | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_MBAR 0xF0000000 |
195 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
196 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
138ff60c | 197 | |
5fb6d719 MB |
198 | /* |
199 | * SDRAM controller configuration | |
200 | */ | |
201 | #undef CONFIG_SDR_MT48LC16M16A2 | |
202 | #undef CONFIG_DDR_MT46V16M16 | |
203 | #undef CONFIG_DDR_MT46V32M16 | |
204 | #undef CONFIG_DDR_HYB25D512160BF | |
205 | #define CONFIG_DDR_K4H511638C | |
138ff60c WD |
206 | |
207 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
800eb096 | 209 | |
138ff60c | 210 | /* preserve space for the post_word at end of on-chip SRAM */ |
800eb096 MZ |
211 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
212 | ||
213 | #ifdef CONFIG_POST | |
553f0982 | 214 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
138ff60c | 215 | #else |
553f0982 | 216 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
138ff60c WD |
217 | #endif |
218 | ||
25ddd1fb | 219 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 220 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
138ff60c | 221 | |
14d0a02a | 222 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
223 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
224 | # define CONFIG_SYS_RAMBOOT 1 | |
138ff60c WD |
225 | #endif |
226 | ||
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
228 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
229 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
138ff60c WD |
230 | |
231 | /* | |
232 | * Ethernet configuration | |
233 | */ | |
234 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 235 | #define CONFIG_MPC5xxx_FEC_MII100 |
138ff60c | 236 | /* |
86321fc1 | 237 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
138ff60c | 238 | */ |
86321fc1 | 239 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
138ff60c | 240 | #define CONFIG_PHY_ADDR 0x00 |
84e106c0 | 241 | #define CONFIG_MII |
138ff60c WD |
242 | |
243 | /* | |
244 | * GPIO configuration | |
245 | * | |
9f709b6c WD |
246 | * use CS1 as gpio_wkup_6 output |
247 | * Bit 0 (mask: 0x80000000): 0 | |
138ff60c WD |
248 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
249 | * 00 -> No Alternatives, I2C1 is used for onboard EEPROM | |
250 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard | |
251 | * EEPROM | |
252 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
e979e85f DZ |
253 | * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 |
254 | * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 | |
255 | * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 | |
138ff60c | 256 | */ |
e979e85f | 257 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 |
138ff60c WD |
258 | |
259 | /* | |
260 | * RTC configuration | |
261 | */ | |
e979e85f DZ |
262 | #define CONFIG_RTC_RTC4543 1 /* use external RTC */ |
263 | ||
264 | /* | |
265 | * Software (bit-bang) three wire serial configuration | |
266 | * | |
267 | * Note that we need the ifdefs because otherwise compilation of | |
268 | * mkimage.c fails. | |
269 | */ | |
270 | #define CONFIG_SOFT_TWS 1 | |
271 | ||
272 | #ifdef TWS_IMPLEMENTATION | |
273 | #include <mpc5xxx.h> | |
274 | #include <asm/io.h> | |
275 | ||
276 | #define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */ | |
277 | #define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */ | |
278 | #define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */ | |
279 | #define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */ | |
280 | ||
281 | static inline void tws_ce(unsigned bit) | |
282 | { | |
283 | struct mpc5xxx_wu_gpio *wu_gpio = | |
284 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
285 | if (bit) | |
286 | setbits_8(&wu_gpio->dvo, TWS_CE); | |
287 | else | |
288 | clrbits_8(&wu_gpio->dvo, TWS_CE); | |
289 | } | |
290 | ||
291 | static inline void tws_wr(unsigned bit) | |
292 | { | |
293 | struct mpc5xxx_wu_gpio *wu_gpio = | |
294 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
295 | if (bit) | |
296 | setbits_8(&wu_gpio->dvo, TWS_WR); | |
297 | else | |
298 | clrbits_8(&wu_gpio->dvo, TWS_WR); | |
299 | } | |
300 | ||
301 | static inline void tws_clk(unsigned bit) | |
302 | { | |
303 | struct mpc5xxx_gpio *gpio = | |
304 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
305 | if (bit) | |
306 | setbits_8(&gpio->sint_dvo, TWS_CLK); | |
307 | else | |
308 | clrbits_8(&gpio->sint_dvo, TWS_CLK); | |
309 | } | |
310 | ||
311 | static inline void tws_data(unsigned bit) | |
312 | { | |
313 | struct mpc5xxx_gpio *gpio = | |
314 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
315 | if (bit) | |
316 | setbits_8(&gpio->sint_dvo, TWS_DATA); | |
317 | else | |
318 | clrbits_8(&gpio->sint_dvo, TWS_DATA); | |
319 | } | |
320 | ||
321 | static inline unsigned tws_data_read(void) | |
322 | { | |
323 | struct mpc5xxx_gpio *gpio = | |
324 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
325 | return !!(in_8(&gpio->sint_ival) & TWS_DATA); | |
326 | } | |
327 | ||
328 | static inline void tws_data_config_output(unsigned output) | |
329 | { | |
330 | struct mpc5xxx_gpio *gpio = | |
331 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
332 | if (output) | |
333 | setbits_8(&gpio->sint_ddr, TWS_DATA); | |
334 | else | |
335 | clrbits_8(&gpio->sint_ddr, TWS_DATA); | |
336 | } | |
337 | #endif /* TWS_IMPLEMENTATION */ | |
138ff60c WD |
338 | |
339 | /* | |
340 | * Miscellaneous configurable options | |
341 | */ | |
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
343 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
1d2c6bc4 | 344 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 345 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
138ff60c | 346 | #else |
6d0f6bcf | 347 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
138ff60c | 348 | #endif |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
350 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
351 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
138ff60c | 352 | |
6d0f6bcf | 353 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
1d2c6bc4 | 354 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 355 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
1d2c6bc4 JL |
356 | #endif |
357 | ||
138ff60c | 358 | /* Enable an alternate, more extensive memory test */ |
6d0f6bcf | 359 | #define CONFIG_SYS_ALT_MEMTEST |
138ff60c | 360 | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
362 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
138ff60c | 363 | |
6d0f6bcf | 364 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
138ff60c | 365 | |
6d0f6bcf | 366 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
138ff60c WD |
367 | |
368 | /* | |
7f5c0157 | 369 | * Enable loopw command. |
138ff60c WD |
370 | */ |
371 | #define CONFIG_LOOPW | |
372 | ||
373 | /* | |
374 | * Various low-level settings | |
375 | */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
377 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
138ff60c | 378 | |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
380 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
381 | #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ | |
382 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
383 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
138ff60c | 384 | |
e58cf2a0 | 385 | /* 32Mbit SRAM @0x30000000 */ |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_CS1_START 0x30000000 |
387 | #define CONFIG_SYS_CS1_SIZE 0x00400000 | |
388 | #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 WD |
389 | |
390 | /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_CS2_START 0x80000000 |
392 | #define CONFIG_SYS_CS2_SIZE 0x0001000 | |
393 | #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 | 394 | |
f4733a07 | 395 | /* GPIO in @0x30400000 */ |
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_CS3_START 0x30400000 |
397 | #define CONFIG_SYS_CS3_SIZE 0x00100000 | |
398 | #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
f4733a07 | 399 | |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_CS_BURST 0x00000000 |
401 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
138ff60c | 402 | |
436be29c WD |
403 | /*----------------------------------------------------------------------- |
404 | * USB stuff | |
405 | *----------------------------------------------------------------------- | |
406 | */ | |
407 | #define CONFIG_USB_OHCI | |
151ab83a WD |
408 | #define CONFIG_USB_CLOCK 0x00015555 |
409 | #define CONFIG_USB_CONFIG 0x00001000 | |
1968e615 | 410 | #define CONFIG_USB_STORAGE |
436be29c | 411 | |
b05dcb58 WD |
412 | /*----------------------------------------------------------------------- |
413 | * IDE/ATA stuff Supports IDE harddisk | |
414 | *----------------------------------------------------------------------- | |
415 | */ | |
416 | ||
417 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
418 | ||
419 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
420 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
421 | ||
b05dcb58 WD |
422 | #define CONFIG_IDE_PREINIT |
423 | ||
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
425 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
b05dcb58 | 426 | |
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
428 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
429 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ | |
430 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ | |
431 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ | |
432 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
b05dcb58 WD |
433 | |
434 | #define CONFIG_ATAPI 1 | |
1806c759 | 435 | |
6d0f6bcf | 436 | #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ |
b05dcb58 | 437 | |
138ff60c | 438 | #endif /* __CONFIG_H */ |