[people/ms/u-boot.git] / include / configs / inka4x0.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CFG_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EXT2	| \
				CFG_CMD_FAT	| \
				CFG_CMD_IDE	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_SNTP	| \
				CFG_CMD_USB	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFE00000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBSPEED_133		/* define for 133MHz speed */

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFFE00000

#define CFG_FLASH_SIZE		0x00200000 /* 2 MByte */
#define CFG_MAX_FLASH_SECT	35	/* max num of sects on one chip */

#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000) /* second sector */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x2000
#define CFG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

#define CONFIG_MPC5200_DDR

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use CS1 as gpio_wkup_6 output
 *	Bit 0 (mask: 0x80000000): 0
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
 *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 */
#define CFG_GPS_PORT_CONFIG	0x01001004

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* 32Mbit SRAM @0x30000000 */
#define CFG_CS1_START		0x30000000
#define CFG_CS1_SIZE		0x00400000
#define CFG_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */

/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CFG_CS2_START		0x80000000
#define CFG_CS2_SIZE		0x0001000
#define CFG_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */

/* GPIO in @0x30400000 */
#define CFG_CS3_START		0x30400000
#define CFG_CS3_SIZE		0x00100000
#define CFG_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_CLOCK	0x00015555
#define CONFIG_USB_CONFIG	0x00001000
#define CONFIG_USB_STORAGE

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#define CONFIG_ATAPI            1
#define CFG_BRIGHTNESS          0x20

#endif /* __CONFIG_H */
Commit	Line	Data
138ff60c	1	/*
414eec35	2	* (C) Copyright 2003-2005
138ff60c WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
151ab83a WD	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	34	#define CONFIG_INKA4X0 1 /* INKA4x0 board */
138ff60c	35
151ab83a	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
138ff60c	37
151ab83a WD	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
151ab83a WD	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
138ff60c	40
151ab83a WD	41	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
	42
	43	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
138ff60c	44	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
151ab83a	45	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
138ff60c WD	46	#endif
	47
	48	/*
	49	* Serial console configuration
	50	*/
151ab83a WD	51	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
151ab83a WD	52	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
138ff60c WD	53	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
138ff60c WD	54
436be29c WD	55	/*
	56	* PCI Mapping:
	57	* 0x40000000 - 0x4fffffff - PCI Memory
	58	* 0x50000000 - 0x50ffffff - PCI IO Space
	59	*/
	60	#define CONFIG_PCI 1
	61	#define CONFIG_PCI_PNP 1
	62	#define CONFIG_PCI_SCAN_SHOW 1
	63
	64	#define CONFIG_PCI_MEM_BUS 0x40000000
	65	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	66	#define CONFIG_PCI_MEM_SIZE 0x10000000
	67
	68	#define CONFIG_PCI_IO_BUS 0x50000000
	69	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	70	#define CONFIG_PCI_IO_SIZE 0x01000000
	71
	72	#define CFG_XLB_PIPELINING 1
	73
	74	/* Partitions */
	75	#define CONFIG_MAC_PARTITION
	76	#define CONFIG_DOS_PARTITION
	77	#define CONFIG_ISO_PARTITION
	78
138ff60c WD	79	/*
	80	* Supported commands
	81	*/
436be29c	82	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
414eec35	83	CFG_CMD_DHCP \| \
b05dcb58 WD	84	CFG_CMD_EXT2 \| \
	85	CFG_CMD_FAT \| \
	86	CFG_CMD_IDE \| \
414eec35	87	CFG_CMD_NFS \| \
436be29c	88	CFG_CMD_PCI \| \
414eec35	89	CFG_CMD_SNTP \| \
436be29c	90	CFG_CMD_USB )
138ff60c WD	91
	92	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	93	#include <cmd_confdefs.h>
	94
b05dcb58 WD	95	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
b05dcb58 WD	96
138ff60c WD	97	#if (TEXT_BASE == 0xFFE00000) /* Boot low */
	98	# define CFG_LOWBOOT 1
	99	#endif
	100
	101	/*
	102	* Autobooting
	103	*/
	104	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	105
	106	#define CONFIG_PREBOOT "echo;" \
	107	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	108	"echo"
	109
	110	#undef CONFIG_BOOTARGS
	111
	112	#define CONFIG_EXTRA_ENV_SETTINGS \
	113	"netdev=eth0\0" \
	114	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	115	"nfsroot=$(serverip):$(rootpath)\0" \
	116	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	117	"addip=setenv bootargs $(bootargs) " \
	118	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	119	":$(hostname):$(netdev):off panic=1\0" \
	120	"flash_nfs=run nfsargs addip;" \
	121	"bootm $(kernel_addr)\0" \
138ff60c	122	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
08f27278	123	"rootpath=/opt/eldk/ppc_82xx\0" \
138ff60c WD	124	""
	125
	126	#define CONFIG_BOOTCOMMAND "run net_nfs"
	127
	128	/*
	129	* IPB Bus clocking configuration.
	130	*/
	131	#define CFG_IPBSPEED_133 /* define for 133MHz speed */
	132
	133	/*
	134	* Flash configuration
	135	*/
	136	#define CFG_FLASH_BASE 0xFFE00000
	137
	138	#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
	139	#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
	140
	141	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
	142	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	143	(= chip selects) */
	144	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	145	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	146
	147	/*
	148	* Environment settings
	149	*/
	150	#define CFG_ENV_IS_IN_FLASH 1
	151	#define CFG_ENV_SIZE 0x2000
	152	#define CFG_ENV_SECT_SIZE 0x2000
	153	#define CONFIG_ENV_OVERWRITE 1
	154
	155	/*
	156	* Memory map
	157	*/
	158	#define CFG_MBAR 0xF0000000
	159	#define CFG_SDRAM_BASE 0x00000000
	160	#define CFG_DEFAULT_MBAR 0x80000000
	161
	162	#define CONFIG_MPC5200_DDR
	163
	164	/* Use ON-Chip SRAM until RAM will be available */
	165	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	166	#ifdef CONFIG_POST
	167	/* preserve space for the post_word at end of on-chip SRAM */
	168	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	169	#else
	170	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	171	#endif
	172
	173
	174	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	175	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	176	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	177
	178	#define CFG_MONITOR_BASE TEXT_BASE
	179	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	180	# define CFG_RAMBOOT 1
	181	#endif
	182
	183	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	184	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	185	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	186
	187	/*
188	* Ethernet configuration
189	*/
190	#define CONFIG_MPC5xxx_FEC 1
191	/*
192	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
193	*/
194	/* #define CONFIG_FEC_10MBIT 1 */
195	#define CONFIG_PHY_ADDR 0x00
196
197	/*
198	* GPIO configuration
199	*
9f709b6c WD	200	* use CS1 as gpio_wkup_6 output
9f709b6c WD	201	* Bit 0 (mask: 0x80000000): 0
138ff60c WD	202	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	203	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
	204	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
	205	* EEPROM
	206	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
	207	* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
	208	* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
138ff60c	209	*/
9f709b6c	210	#define CFG_GPS_PORT_CONFIG 0x01001004
138ff60c WD	211
	212	/*
	213	* RTC configuration
	214	*/
	215	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	216
	217	/*
	218	* Miscellaneous configurable options
	219	*/
	220	#define CFG_LONGHELP /* undef to save memory */
	221	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	222	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	223	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	224	#else
	225	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	226	#endif
	227	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	228	#define CFG_MAXARGS 16 /* max number of command args */
	229	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	230
	231	/* Enable an alternate, more extensive memory test */
	232	#define CFG_ALT_MEMTEST
	233
	234	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	235	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	236
	237	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	238
	239	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	240
	241	/*
	242	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
	243	* which is normally part of the default commands (CFV_CMD_DFL)
	244	*/
	245	#define CONFIG_LOOPW
	246
	247	/*
	248	* Various low-level settings
	249	*/
	250	#if defined(CONFIG_MPC5200)
	251	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	252	#define CFG_HID0_FINAL HID0_ICE
	253	#else
	254	#define CFG_HID0_INIT 0
	255	#define CFG_HID0_FINAL 0
	256	#endif
	257
	258	#define CFG_BOOTCS_START CFG_FLASH_BASE
	259	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	260	#define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
	261	#define CFG_CS0_START CFG_FLASH_BASE
	262	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	263
e58cf2a0 WD	264	/* 32Mbit SRAM @0x30000000 */
	265	#define CFG_CS1_START 0x30000000
	266	#define CFG_CS1_SIZE 0x00400000
	267	#define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
	268
	269	/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
	270	#define CFG_CS2_START 0x80000000
	271	#define CFG_CS2_SIZE 0x0001000
	272	#define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
	273
f4733a07 WD	274	/* GPIO in @0x30400000 */
	275	#define CFG_CS3_START 0x30400000
	276	#define CFG_CS3_SIZE 0x00100000
	277	#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
	278
138ff60c WD	279	#define CFG_CS_BURST 0x00000000
	280	#define CFG_CS_DEADCYCLE 0x33333333
	281
436be29c WD	282	/*-----------------------------------------------------------------------
	283	* USB stuff
	284	*-----------------------------------------------------------------------
	285	*/
	286	#define CONFIG_USB_OHCI
151ab83a WD	287	#define CONFIG_USB_CLOCK 0x00015555
151ab83a WD	288	#define CONFIG_USB_CONFIG 0x00001000
1968e615	289	#define CONFIG_USB_STORAGE
436be29c	290
b05dcb58 WD	291	/*-----------------------------------------------------------------------
	292	* IDE/ATA stuff Supports IDE harddisk
	293	*-----------------------------------------------------------------------
	294	*/
	295
	296	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	297
	298	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	299	#undef CONFIG_IDE_LED /* LED for ide not supported */
	300
	301	#define CONFIG_IDE_RESET /* reset for ide supported */
	302	#define CONFIG_IDE_PREINIT
	303
	304	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	305	#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
	306
	307	#define CFG_ATA_IDE0_OFFSET 0x0000
	308
	309	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	310
	311	/* Offset for data I/O */
	312	#define CFG_ATA_DATA_OFFSET (0x0060)
	313
	314	/* Offset for normal register accesses */
	315	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	316
	317	/* Offset for alternate registers */
	318	#define CFG_ATA_ALT_OFFSET (0x005C)
	319
	320	/* Interval between registers */
	321	#define CFG_ATA_STRIDE 4
	322
	323	#define CONFIG_ATAPI 1
a0bdf49e	324	#define CFG_BRIGHTNESS 0x20
b05dcb58	325
138ff60c	326	#endif /* __CONFIG_H */