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Commit | Line | Data |
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138ff60c | 1 | /* |
e979e85f DZ |
2 | * (C) Copyright 2009 |
3 | * Detlev Zundel, DENX Software Engineering, dzu@denx.de. | |
4 | * | |
414eec35 | 5 | * (C) Copyright 2003-2005 |
138ff60c WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
138ff60c WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 MY |
19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
20 | #define CONFIG_INKA4X0 1 /* INKA4x0 board */ | |
c8298935 | 21 | #define CONFIG_DISPLAY_BOARDINFO |
138ff60c | 22 | |
2ae18241 WD |
23 | /* |
24 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
25 | * 0xFFE00000 boot low | |
26 | * 0x00100000 boot from RAM (for testing only) | |
27 | */ | |
28 | #ifndef CONFIG_SYS_TEXT_BASE | |
29 | #define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ | |
30 | #endif | |
2ced53e1 | 31 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" |
2ae18241 | 32 | |
6d0f6bcf | 33 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
138ff60c | 34 | |
151ab83a WD |
35 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
36 | ||
31d82672 BB |
37 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
38 | ||
138ff60c WD |
39 | /* |
40 | * Serial console configuration | |
41 | */ | |
151ab83a WD |
42 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
43 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 44 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
138ff60c | 45 | |
436be29c WD |
46 | /* |
47 | * PCI Mapping: | |
48 | * 0x40000000 - 0x4fffffff - PCI Memory | |
49 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
50 | */ | |
51 | #define CONFIG_PCI 1 | |
52 | #define CONFIG_PCI_PNP 1 | |
53 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 54 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
436be29c WD |
55 | |
56 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
57 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
58 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
59 | ||
60 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
61 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
62 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
63 | ||
6d0f6bcf | 64 | #define CONFIG_SYS_XLB_PIPELINING 1 |
436be29c WD |
65 | |
66 | /* Partitions */ | |
67 | #define CONFIG_MAC_PARTITION | |
68 | #define CONFIG_DOS_PARTITION | |
69 | #define CONFIG_ISO_PARTITION | |
70 | ||
1d2c6bc4 | 71 | |
7f5c0157 JL |
72 | /* |
73 | * BOOTP options | |
74 | */ | |
75 | #define CONFIG_BOOTP_BOOTFILESIZE | |
76 | #define CONFIG_BOOTP_BOOTPATH | |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_HOSTNAME | |
79 | ||
80 | ||
138ff60c | 81 | /* |
1d2c6bc4 | 82 | * Command line configuration. |
138ff60c | 83 | */ |
e979e85f | 84 | #define CONFIG_CMD_DATE |
1d2c6bc4 JL |
85 | #define CONFIG_CMD_EXT2 |
86 | #define CONFIG_CMD_FAT | |
87 | #define CONFIG_CMD_IDE | |
1d2c6bc4 | 88 | #define CONFIG_CMD_PCI |
1d2c6bc4 | 89 | |
b05dcb58 WD |
90 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
91 | ||
14d0a02a | 92 | #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ |
6d0f6bcf | 93 | # define CONFIG_SYS_LOWBOOT 1 |
138ff60c WD |
94 | #endif |
95 | ||
96 | /* | |
97 | * Autobooting | |
98 | */ | |
84e106c0 | 99 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
138ff60c WD |
100 | |
101 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 102 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
138ff60c WD |
103 | "echo" |
104 | ||
105 | #undef CONFIG_BOOTARGS | |
106 | ||
84e106c0 WD |
107 | #define CONFIG_IPADDR 192.168.100.2 |
108 | #define CONFIG_SERVERIP 192.168.100.1 | |
109 | #define CONFIG_NETMASK 255.255.255.0 | |
110 | #define HOSTNAME inka4x0 | |
b3f44c21 | 111 | #define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage" |
8b3637c6 | 112 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
84e106c0 | 113 | |
138ff60c WD |
114 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
115 | "netdev=eth0\0" \ | |
116 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 117 | "nfsroot=${serverip}:${rootpath}\0" \ |
138ff60c | 118 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
119 | "addip=setenv bootargs ${bootargs} " \ |
120 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
121 | ":${hostname}:${netdev}:off panic=1\0" \ | |
84e106c0 WD |
122 | "addcons=setenv bootargs ${bootargs} " \ |
123 | "console=ttyS0,${baudrate}\0" \ | |
124 | "flash_nfs=run nfsargs addip addcons;" \ | |
fe126d8b | 125 | "bootm ${kernel_addr}\0" \ |
84e106c0 WD |
126 | "net_nfs=tftp 200000 ${bootfile};" \ |
127 | "run nfsargs addip addcons;bootm\0" \ | |
128 | "enable_disp=mw.l 100000 04000000 1;" \ | |
129 | "cp.l 100000 f0000b20 1;" \ | |
130 | "cp.l 100000 f0000b28 1\0" \ | |
131 | "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ | |
132 | "ide_boot=ext2load ide 0:1 200000 uImage;" \ | |
f23cb34c | 133 | "run ideargs addip addcons enable_disp;bootm\0" \ |
84e106c0 | 134 | "brightness=255\0" \ |
138ff60c WD |
135 | "" |
136 | ||
84e106c0 | 137 | #define CONFIG_BOOTCOMMAND "run ide_boot" |
138ff60c WD |
138 | |
139 | /* | |
140 | * IPB Bus clocking configuration. | |
141 | */ | |
6d0f6bcf | 142 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
138ff60c WD |
143 | |
144 | /* | |
145 | * Flash configuration | |
146 | */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 148 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
150 | #define CONFIG_SYS_FLASH_SIZE 0x00200000 | |
151 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
152 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
153 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
154 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
138ff60c WD |
155 | |
156 | /* | |
157 | * Environment settings | |
158 | */ | |
5a1aceb0 | 159 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 160 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) |
0e8d1586 JCPV |
161 | #define CONFIG_ENV_SIZE 0x2000 |
162 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
138ff60c | 163 | #define CONFIG_ENV_OVERWRITE 1 |
6d0f6bcf | 164 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
138ff60c WD |
165 | |
166 | /* | |
167 | * Memory map | |
168 | */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MBAR 0xF0000000 |
170 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
171 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
138ff60c | 172 | |
5fb6d719 MB |
173 | /* |
174 | * SDRAM controller configuration | |
175 | */ | |
176 | #undef CONFIG_SDR_MT48LC16M16A2 | |
177 | #undef CONFIG_DDR_MT46V16M16 | |
178 | #undef CONFIG_DDR_MT46V32M16 | |
179 | #undef CONFIG_DDR_HYB25D512160BF | |
180 | #define CONFIG_DDR_K4H511638C | |
138ff60c WD |
181 | |
182 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
800eb096 | 184 | |
138ff60c | 185 | /* preserve space for the post_word at end of on-chip SRAM */ |
800eb096 MZ |
186 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
187 | ||
188 | #ifdef CONFIG_POST | |
553f0982 | 189 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
138ff60c | 190 | #else |
553f0982 | 191 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
138ff60c WD |
192 | #endif |
193 | ||
25ddd1fb | 194 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 195 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
138ff60c | 196 | |
14d0a02a | 197 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
198 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
199 | # define CONFIG_SYS_RAMBOOT 1 | |
138ff60c WD |
200 | #endif |
201 | ||
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
203 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
204 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
138ff60c WD |
205 | |
206 | /* | |
207 | * Ethernet configuration | |
208 | */ | |
209 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 210 | #define CONFIG_MPC5xxx_FEC_MII100 |
138ff60c | 211 | /* |
86321fc1 | 212 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
138ff60c | 213 | */ |
86321fc1 | 214 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
138ff60c | 215 | #define CONFIG_PHY_ADDR 0x00 |
84e106c0 | 216 | #define CONFIG_MII |
138ff60c WD |
217 | |
218 | /* | |
219 | * GPIO configuration | |
220 | * | |
9f709b6c WD |
221 | * use CS1 as gpio_wkup_6 output |
222 | * Bit 0 (mask: 0x80000000): 0 | |
138ff60c WD |
223 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
224 | * 00 -> No Alternatives, I2C1 is used for onboard EEPROM | |
225 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard | |
226 | * EEPROM | |
227 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
e979e85f DZ |
228 | * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 |
229 | * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 | |
230 | * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 | |
138ff60c | 231 | */ |
e979e85f | 232 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 |
138ff60c WD |
233 | |
234 | /* | |
235 | * RTC configuration | |
236 | */ | |
e979e85f DZ |
237 | #define CONFIG_RTC_RTC4543 1 /* use external RTC */ |
238 | ||
239 | /* | |
240 | * Software (bit-bang) three wire serial configuration | |
241 | * | |
242 | * Note that we need the ifdefs because otherwise compilation of | |
243 | * mkimage.c fails. | |
244 | */ | |
245 | #define CONFIG_SOFT_TWS 1 | |
246 | ||
247 | #ifdef TWS_IMPLEMENTATION | |
248 | #include <mpc5xxx.h> | |
249 | #include <asm/io.h> | |
250 | ||
251 | #define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */ | |
252 | #define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */ | |
253 | #define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */ | |
254 | #define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */ | |
255 | ||
256 | static inline void tws_ce(unsigned bit) | |
257 | { | |
258 | struct mpc5xxx_wu_gpio *wu_gpio = | |
259 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
260 | if (bit) | |
261 | setbits_8(&wu_gpio->dvo, TWS_CE); | |
262 | else | |
263 | clrbits_8(&wu_gpio->dvo, TWS_CE); | |
264 | } | |
265 | ||
266 | static inline void tws_wr(unsigned bit) | |
267 | { | |
268 | struct mpc5xxx_wu_gpio *wu_gpio = | |
269 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
270 | if (bit) | |
271 | setbits_8(&wu_gpio->dvo, TWS_WR); | |
272 | else | |
273 | clrbits_8(&wu_gpio->dvo, TWS_WR); | |
274 | } | |
275 | ||
276 | static inline void tws_clk(unsigned bit) | |
277 | { | |
278 | struct mpc5xxx_gpio *gpio = | |
279 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
280 | if (bit) | |
281 | setbits_8(&gpio->sint_dvo, TWS_CLK); | |
282 | else | |
283 | clrbits_8(&gpio->sint_dvo, TWS_CLK); | |
284 | } | |
285 | ||
286 | static inline void tws_data(unsigned bit) | |
287 | { | |
288 | struct mpc5xxx_gpio *gpio = | |
289 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
290 | if (bit) | |
291 | setbits_8(&gpio->sint_dvo, TWS_DATA); | |
292 | else | |
293 | clrbits_8(&gpio->sint_dvo, TWS_DATA); | |
294 | } | |
295 | ||
296 | static inline unsigned tws_data_read(void) | |
297 | { | |
298 | struct mpc5xxx_gpio *gpio = | |
299 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
300 | return !!(in_8(&gpio->sint_ival) & TWS_DATA); | |
301 | } | |
302 | ||
303 | static inline void tws_data_config_output(unsigned output) | |
304 | { | |
305 | struct mpc5xxx_gpio *gpio = | |
306 | (struct mpc5xxx_gpio *)MPC5XXX_GPIO; | |
307 | if (output) | |
308 | setbits_8(&gpio->sint_ddr, TWS_DATA); | |
309 | else | |
310 | clrbits_8(&gpio->sint_ddr, TWS_DATA); | |
311 | } | |
312 | #endif /* TWS_IMPLEMENTATION */ | |
138ff60c WD |
313 | |
314 | /* | |
315 | * Miscellaneous configurable options | |
316 | */ | |
6d0f6bcf | 317 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
1d2c6bc4 | 318 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 319 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
138ff60c | 320 | #else |
6d0f6bcf | 321 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
138ff60c | 322 | #endif |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
324 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
325 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
138ff60c | 326 | |
6d0f6bcf | 327 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
1d2c6bc4 | 328 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 329 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
1d2c6bc4 JL |
330 | #endif |
331 | ||
138ff60c | 332 | /* Enable an alternate, more extensive memory test */ |
6d0f6bcf | 333 | #define CONFIG_SYS_ALT_MEMTEST |
138ff60c | 334 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
336 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
138ff60c | 337 | |
6d0f6bcf | 338 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
138ff60c | 339 | |
138ff60c WD |
340 | /* |
341 | * Various low-level settings | |
342 | */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
344 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
138ff60c | 345 | |
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
347 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
348 | #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ | |
349 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
350 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
138ff60c | 351 | |
e58cf2a0 | 352 | /* 32Mbit SRAM @0x30000000 */ |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_CS1_START 0x30000000 |
354 | #define CONFIG_SYS_CS1_SIZE 0x00400000 | |
355 | #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 WD |
356 | |
357 | /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_CS2_START 0x80000000 |
359 | #define CONFIG_SYS_CS2_SIZE 0x0001000 | |
360 | #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ | |
e58cf2a0 | 361 | |
f4733a07 | 362 | /* GPIO in @0x30400000 */ |
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_CS3_START 0x30400000 |
364 | #define CONFIG_SYS_CS3_SIZE 0x00100000 | |
365 | #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ | |
f4733a07 | 366 | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_CS_BURST 0x00000000 |
368 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
138ff60c | 369 | |
436be29c WD |
370 | /*----------------------------------------------------------------------- |
371 | * USB stuff | |
372 | *----------------------------------------------------------------------- | |
373 | */ | |
374 | #define CONFIG_USB_OHCI | |
151ab83a WD |
375 | #define CONFIG_USB_CLOCK 0x00015555 |
376 | #define CONFIG_USB_CONFIG 0x00001000 | |
1968e615 | 377 | #define CONFIG_USB_STORAGE |
436be29c | 378 | |
b05dcb58 WD |
379 | /*----------------------------------------------------------------------- |
380 | * IDE/ATA stuff Supports IDE harddisk | |
381 | *----------------------------------------------------------------------- | |
382 | */ | |
383 | ||
384 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
385 | ||
386 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
387 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
388 | ||
b05dcb58 WD |
389 | #define CONFIG_IDE_PREINIT |
390 | ||
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
392 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
b05dcb58 | 393 | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
395 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
396 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ | |
397 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ | |
398 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ | |
399 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ | |
b05dcb58 WD |
400 | |
401 | #define CONFIG_ATAPI 1 | |
1806c759 | 402 | |
6d0f6bcf | 403 | #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ |
b05dcb58 | 404 | |
138ff60c | 405 | #endif /* __CONFIG_H */ |