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e62b008f LW |
1 | /* |
2 | * (C) Copyright 2012 | |
3 | * Linaro | |
4 | * Linus Walleij <linus.walleij@linaro.org> | |
5 | * Common ARM Integrator configuration settings | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
e62b008f LW |
8 | */ |
9 | ||
e62b008f LW |
10 | #define CONFIG_SYS_TEXT_BASE 0x01000000 |
11 | #define CONFIG_SYS_MEMTEST_START 0x100000 | |
12 | #define CONFIG_SYS_MEMTEST_END 0x10000000 | |
e62b008f LW |
13 | #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ |
14 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ | |
15 | #define CONFIG_SYS_LONGHELP | |
e62b008f LW |
16 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ |
17 | ||
3f394e70 LW |
18 | /* Serial port PL010/PL011 through the device model */ |
19 | #define CONFIG_PL01X_SERIAL | |
3f394e70 LW |
20 | #define CONFIG_CONS_INDEX 0 |
21 | ||
e62b008f LW |
22 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
23 | #define CONFIG_SETUP_MEMORY_TAGS | |
24 | #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ | |
25 | ||
26 | /* | |
27 | * There are various dependencies on the core module (CM) fitted | |
28 | * Users should refer to their CM user guide | |
29 | */ | |
30 | #include "armcoremodule.h" | |
31 | ||
32 | /* | |
33 | * Initialize and remap the core module, use SPD to detect memory size | |
34 | * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & | |
35 | * the core module has a CM_INIT register | |
36 | * then the U-Boot initialisation code will | |
37 | * e.g. ARM Boot Monitor or pre-loader is repeated once | |
38 | * (to re-initialise any existing CM_INIT settings to safe values). | |
39 | * | |
40 | * This is usually not the desired behaviour since the platform | |
41 | * will either reboot into the ARM monitor (or pre-loader) | |
42 | * or continuously cycle thru it without U-Boot running, | |
43 | * depending upon the setting of Integrator/CP switch S2-4. | |
44 | * | |
45 | * However it may be needed if Integrator/CP switch S2-1 | |
46 | * is set OFF to boot direct into U-Boot. | |
47 | * In that case comment out the line below. | |
48 | */ | |
49 | #define CONFIG_CM_INIT | |
50 | #define CONFIG_CM_REMAP | |
51 | #define CONFIG_CM_SPD_DETECT | |
52 | ||
53 | /* | |
54 | * The ARM boot monitor initializes the board. | |
55 | * However, the default U-Boot code also performs the initialization. | |
56 | * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT | |
57 | * - see documentation supplied with board for details of how to choose the | |
58 | * image to run at reset/power up | |
59 | * e.g. whether the ARM Boot Monitor runs before U-Boot | |
60 | */ | |
61 | /* #define CONFIG_SKIP_LOWLEVEL_INIT */ | |
62 | ||
63 | /* | |
64 | * The ARM boot monitor does not relocate U-Boot. | |
65 | * However, the default U-Boot code performs the relocation check, | |
66 | * and may relocate the code if the memory map is changed. | |
67 | * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT | |
68 | */ | |
69 | /* #define SKIP_CONFIG_RELOCATE_UBOOT */ | |
70 | ||
e62b008f LW |
71 | /* |
72 | * Physical Memory Map | |
73 | */ | |
74 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
75 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
76 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ | |
77 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
78 | #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE | |
79 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ | |
80 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
81 | GENERATED_GBL_DATA_SIZE) | |
82 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET | |
a7b00a7b LW |
83 | |
84 | /* | |
85 | * FLASH and environment organization | |
86 | * Top varies according to amount fitted | |
87 | * Reserve top 4 blocks of flash | |
88 | * - ARM Boot Monitor | |
89 | * - Unused | |
90 | * - SIB block | |
91 | * - U-Boot environment | |
92 | */ | |
a7b00a7b LW |
93 | #define CONFIG_SYS_FLASH_CFI 1 |
94 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
95 | #define CONFIG_SYS_FLASH_BASE 0x24000000 | |
96 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
97 | ||
98 | /* Timeout values in ticks */ | |
99 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ | |
100 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ | |
101 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ | |
102 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |