[people/ms/u-boot.git] / include / configs / integratorap.h

/*
 * (C) Copyright 2003
 * Texas Instruments.
 * Kshitij Gupta <kshitij@ti.com>
 * Configuation settings for the TI OMAP Innovator board.
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <philippe.robin@arm.com>
 * Configuration for Integrator AP board.
 *.
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H
/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CFG_MEMTEST_START	0x100000
#define CFG_MEMTEST_END		0x10000000
#define CFG_HZ			1000
#define CFG_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
#define CFG_TIMERBASE		0x13000100	/* Timer1		       */

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */

#undef CONFIG_INIT_CRITICAL
#define CONFIG_CM_INIT		1
#define CONFIG_CM_REMAP		1
#undef CONFIG_CM_SPD_DETECT

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * PL010 Configuration
 */
#define CFG_PL010_SERIAL
#define CONFIG_CONS_INDEX	0
#define CONFIG_BAUDRATE		38400
#define CONFIG_PL01x_PORTS	{ (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0		0x16000000
#define CFG_SERIAL1		0x17000000

/*#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */
/*#define CONFIG_BOOTP_MASK	  CONFIG_BOOTP_DEFAULT */

#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)


/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	2
#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
#define CONFIG_BOOTCOMMAND	""

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP	/* undef to save memory	    */
#define CFG_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
/* Print Buffer Size */
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR	0x7fc0	/* default load address */

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */

#define CFG_FLASH_BASE		0x24000000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_ENV_IS_NOWHERE
#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
#define CFG_MAX_FLASH_SECT	128
#define CFG_ENV_SIZE		32768

#define PHYS_FLASH_1		(CFG_FLASH_BASE)

/*-----------------------------------------------------------------------
 * PCI definitions
 */

/*#define CONFIG_PCI			/--* include pci support	*/
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
#define DEBUG

#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/


#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
#define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000

/* PCI Base area */
#define INTEGRATOR_PCI_BASE		0x40000000
#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF

/* memory map as seen by the CPU on the local bus */
#define CPU_PCI_IO_ADRS		0x60000000	/* PCI I/O space base */
#define CPU_PCI_IO_SIZE		0x10000

#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
#define CPU_PCI_CNFG_SIZE	0x1000000

#define PCI_MEM_BASE		0x40000000   /* 512M to xxx */
/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
#define INTEGRATOR_PCI_IO_BASE	0x60000000   /* 16M to xxx */
/*  unused (128-16)M from B1000000-B7FFFFFF */
#define PCI_CONFIG_BASE		0x61000000   /* 16M to xxx */
/*  unused ((128-16)M - 64K) from XXX */

#define PCI_V3_BASE		0x62000000

/* V3 PCI bridge controller */
#define V3_BASE			0x62000000    /* V360EPC registers */

#define PCI_ENET0_IOADDR	(CPU_PCI_IO_ADRS)
#define PCI_ENET0_MEMADDR	(PCI_MEM_BASE)


#define V3_PCI_VENDOR		0x00000000
#define V3_PCI_DEVICE		0x00000002
#define V3_PCI_CMD		0x00000004
#define V3_PCI_STAT		0x00000006
#define V3_PCI_CC_REV		0x00000008
#define V3_PCI_HDR_CF		0x0000000C
#define V3_PCI_IO_BASE		0x00000010
#define V3_PCI_BASE0		0x00000014
#define V3_PCI_BASE1		0x00000018
#define V3_PCI_SUB_VENDOR	0x0000002C
#define V3_PCI_SUB_ID		0x0000002E
#define V3_PCI_ROM		0x00000030
#define V3_PCI_BPARAM		0x0000003C
#define V3_PCI_MAP0		0x00000040
#define V3_PCI_MAP1		0x00000044
#define V3_PCI_INT_STAT		0x00000048
#define V3_PCI_INT_CFG		0x0000004C
#define V3_LB_BASE0		0x00000054
#define V3_LB_BASE1		0x00000058
#define V3_LB_MAP0		0x0000005E
#define V3_LB_MAP1		0x00000062
#define V3_LB_BASE2		0x00000064
#define V3_LB_MAP2		0x00000066
#define V3_LB_SIZE		0x00000068
#define V3_LB_IO_BASE		0x0000006E
#define V3_FIFO_CFG		0x00000070
#define V3_FIFO_PRIORITY	0x00000072
#define V3_FIFO_STAT		0x00000074
#define V3_LB_ISTAT		0x00000076
#define V3_LB_IMASK		0x00000077
#define V3_SYSTEM		0x00000078
#define V3_LB_CFG		0x0000007A
#define V3_PCI_CFG		0x0000007C
#define V3_DMA_PCI_ADR0		0x00000080
#define V3_DMA_PCI_ADR1		0x00000090
#define V3_DMA_LOCAL_ADR0	0x00000084
#define V3_DMA_LOCAL_ADR1	0x00000094
#define V3_DMA_LENGTH0		0x00000088
#define V3_DMA_LENGTH1		0x00000098
#define V3_DMA_CSR0		0x0000008B
#define V3_DMA_CSR1		0x0000009B
#define V3_DMA_CTLB_ADR0	0x0000008C
#define V3_DMA_CTLB_ADR1	0x0000009C
#define V3_DMA_DELAY		0x000000E0
#define V3_MAIL_DATA		0x000000C0
#define V3_PCI_MAIL_IEWR	0x000000D0
#define V3_PCI_MAIL_IERD	0x000000D2
#define V3_LB_MAIL_IEWR		0x000000D4
#define V3_LB_MAIL_IERD		0x000000D6
#define V3_MAIL_WR_STAT		0x000000D8
#define V3_MAIL_RD_STAT		0x000000DA
#define V3_QBA_MAP		0x000000DC

/* SYSTEM register bits */
#define V3_SYSTEM_M_RST_OUT		(1 << 15)
#define V3_SYSTEM_M_LOCK		(1 << 14)

/*  PCI_CFG bits */
#define V3_PCI_CFG_M_RETRY_EN		(1 << 10)
#define V3_PCI_CFG_M_AD_LOW1		(1 << 9)
#define V3_PCI_CFG_M_AD_LOW0		(1 << 8)

/* PCI MAP register bits (PCI -> Local bus) */
#define V3_PCI_MAP_M_MAP_ADR		0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH	(1 << 15)
#define V3_PCI_MAP_M_ROM_SIZE		(1 << 11 | 1 << 10)
#define V3_PCI_MAP_M_SWAP		(1 << 9 | 1 << 8)
#define V3_PCI_MAP_M_ADR_SIZE		0x000000F0
#define V3_PCI_MAP_M_REG_EN		(1 << 1)
#define V3_PCI_MAP_M_ENABLE		(1 << 0)

/* 9 => 512M window size */
#define V3_PCI_MAP_M_ADR_SIZE_512M	0x00000090

/* A => 1024M window size */
#define V3_PCI_MAP_M_ADR_SIZE_1024M	0x000000A0

/* LB_BASE register bits (Local bus -> PCI) */
#define V3_LB_BASE_M_MAP_ADR		0xFFF00000
#define V3_LB_BASE_M_SWAP		(1 << 8 | 1 << 9)
#define V3_LB_BASE_M_ADR_SIZE		0x000000F0
#define V3_LB_BASE_M_PREFETCH		(1 << 3)
#define V3_LB_BASE_M_ENABLE		(1 << 0)

/* PCI COMMAND REGISTER bits */
#define V3_COMMAND_M_FBB_EN		(1 << 9)
#define V3_COMMAND_M_SERR_EN		(1 << 8)
#define V3_COMMAND_M_PAR_EN		(1 << 6)
#define V3_COMMAND_M_MASTER_EN		(1 << 2)
#define V3_COMMAND_M_MEM_EN		(1 << 1)
#define V3_COMMAND_M_IO_EN		(1 << 0)

#define INTEGRATOR_SC_BASE		0x11000000
#define INTEGRATOR_SC_PCIENABLE_OFFSET	0x18
#define INTEGRATOR_SC_PCIENABLE \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)

/*-----------------------------------------------------------------------
 * There are various dependencies on the core module (CM) fitted
 * Users should refer to their CM user guide
 * - when porting adjust u-boot/Makefile accordingly
 *   to define the necessary CONFIG_ s for the CM involved
 * see e.g. integratorcp_CM926EJ-S_config
 */

#define CM_BASE		0x10000000

/* CM registers common to all integrator/CP CMs */
#define OS_CTRL			0x0000000C
#define CMMASK_REMAP		0x00000005	/* Set remap & led	     */
#define CMMASK_RESET		0x00000008
#define OS_LOCK			0x00000014
#define CMVAL_LOCK		0x0000A000	/* Locking value	     */
#define CMMASK_LOCK		0x0000005F	/* Locking value	     */
#define CMVAL_UNLOCK		0x00000000	/* Any value != CM_LOCKVAL   */
#define OS_SDRAM		0x00000020
#define OS_INIT			0x00000024
#define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
#define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
#define CMMASK_LOWVEC	      0x00000004      /* vectors @ 0x00000000 */

#ifdef CONFIG_CM_SPD_DETECT
#define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
#endif

#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
#define CMMASK_INIT_102	      0x00000300      /* see CM102xx ref manual
					       * - PLL test clock bypassed
					       * - bus clock ratio 2
					       * - little endian
					       * - vectors at zero
					       */
#endif /* CM1022xx */

#define CMMASK_LE	      0x00000008      /* little endian */
#define CMMASK_CMxx6_COMMON   0x00000100      /* Common value for CMxx6
					       * - divisor/ratio b00000001
					       *		 bx
					       * - HCLKDIV	 b000
					       *		 bxx
					       * - PLL BYPASS	 b00
					       */
#endif	/* __CONFIG_H */
Commit	Line	Data
3d3befa7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Texas Instruments.
	4	* Kshitij Gupta <kshitij@ti.com>
	5	* Configuation settings for the TI OMAP Innovator board.
	6	*
	7	* (C) Copyright 2004
	8	* ARM Ltd.
	9	* Philippe Robin, <philippe.robin@arm.com>
	10	* Configuration for Integrator AP board.
	11	*.
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
fe7eb5d8	30
3d3befa7 WD	31	#ifndef __CONFIG_H
3d3befa7 WD	32	#define __CONFIG_H
3d3befa7 WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
74f4304e WD	37	#define CFG_MEMTEST_START 0x100000
	38	#define CFG_MEMTEST_END 0x10000000
	39	#define CFG_HZ 1000
	40	#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
716c1dcb	41	#define CFG_TIMERBASE 0x13000100 /* Timer1 */
3d3befa7 WD	42
	43	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS 1
	45	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
0148e8cb WD	46
0148e8cb WD	47	#undef CONFIG_INIT_CRITICAL
716c1dcb WD	48	#define CONFIG_CM_INIT 1
716c1dcb WD	49	#define CONFIG_CM_REMAP 1
0148e8cb WD	50	#undef CONFIG_CM_SPD_DETECT
0148e8cb WD	51
3d3befa7 WD	52	/*
	53	* Size of malloc() pool
	54	*/
	55	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
42dfe7a1	56	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
3d3befa7 WD	57
	58	/*
	59	* PL010 Configuration
	60	*/
	61	#define CFG_PL010_SERIAL
	62	#define CONFIG_CONS_INDEX 0
716c1dcb	63	#define CONFIG_BAUDRATE 38400
6705d81e	64	#define CONFIG_PL01x_PORTS { (void ) (CFG_SERIAL0), (void ) (CFG_SERIAL1) }
716c1dcb	65	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3d3befa7 WD	66	#define CFG_SERIAL0 0x16000000
	67	#define CFG_SERIAL1 0x17000000
	68
42dfe7a1 WD	69	/#define CONFIG_COMMANDS (CFG_CMD_DHCP \| CFG_CMD_IMI \| CFG_CMD_NET \| CFG_CMD_PING \| CFG_CMD_BDI \| CFG_CMD_PCI) /
42dfe7a1 WD	70	/#define CONFIG_NET_MULTI /
716c1dcb	71	/#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /
3d3befa7	72
716c1dcb	73	#define CONFIG_COMMANDS (CFG_CMD_IMI \| CFG_CMD_BDI \| CFG_CMD_MEMORY)
3d3befa7 WD	74
	75
	76	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	77	#include <cmd_confdefs.h>
	78
716c1dcb WD	79	#define CONFIG_BOOTDELAY 2
	80	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
	81	#define CONFIG_BOOTCOMMAND ""
3d3befa7 WD	82
	83	/*
	84	* Miscellaneous configurable options
	85	*/
716c1dcb	86	#define CFG_LONGHELP /* undef to save memory */
3d3befa7 WD	87	#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
	88	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	89	/* Print Buffer Size */
	90	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
716c1dcb WD	91	#define CFG_MAXARGS 16 /* max number of command args */
716c1dcb WD	92	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
3d3befa7 WD	93
	94	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	95	#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
	96
	97	/*-----------------------------------------------------------------------
	98	* Stack sizes
	99	*
	100	* The stack sizes are set up in start.S using the settings below
	101	*/
	102	#define CONFIG_STACKSIZE (1281024) / regular stack */
	103	#ifdef CONFIG_USE_IRQ
	104	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	105	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	106	#endif
	107
	108	/*-----------------------------------------------------------------------
	109	* Physical Memory Map
	110	*/
716c1dcb WD	111	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
716c1dcb WD	112	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
3d3befa7 WD	113	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
3d3befa7 WD	114
716c1dcb	115	#define CFG_FLASH_BASE 0x24000000
3d3befa7 WD	116
	117	/*-----------------------------------------------------------------------
	118	* FLASH and environment organization
	119	*/
	120	#define CFG_ENV_IS_NOWHERE
	121	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	122	#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
	123	/* timeout values are in ticks */
74f4304e WD	124	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
74f4304e WD	125	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
716c1dcb WD	126	#define CFG_MAX_FLASH_SECT 128
716c1dcb WD	127	#define CFG_ENV_SIZE 32768
3d3befa7 WD	128
	129	#define PHYS_FLASH_1 (CFG_FLASH_BASE)
	130
	131	/*-----------------------------------------------------------------------
	132	* PCI definitions
	133	*/
	134
74f4304e	135	/#define CONFIG_PCI /-- include pci support */
3d3befa7	136	#undef CONFIG_PCI_PNP
716c1dcb	137	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
3d3befa7 WD	138	#define DEBUG
	139
	140	#define CONFIG_EEPRO100
716c1dcb	141	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
3d3befa7 WD	142
	143
	144	#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
716c1dcb	145	#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
3d3befa7	146
42dfe7a1	147	/* PCI Base area */
3d3befa7 WD	148	#define INTEGRATOR_PCI_BASE 0x40000000
	149	#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
	150
42dfe7a1	151	/* memory map as seen by the CPU on the local bus */
716c1dcb	152	#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
42dfe7a1	153	#define CPU_PCI_IO_SIZE 0x10000
3d3befa7	154
42dfe7a1	155	#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
3d3befa7 WD	156	#define CPU_PCI_CNFG_SIZE 0x1000000
3d3befa7 WD	157
716c1dcb	158	#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
42dfe7a1	159	/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
716c1dcb	160	#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
42dfe7a1	161	/* unused (128-16)M from B1000000-B7FFFFFF */
716c1dcb	162	#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
42dfe7a1	163	/* unused ((128-16)M - 64K) from XXX */
3d3befa7	164
716c1dcb	165	#define PCI_V3_BASE 0x62000000
3d3befa7	166
42dfe7a1 WD	167	/* V3 PCI bridge controller */
42dfe7a1 WD	168	#define V3_BASE 0x62000000 /* V360EPC registers */
3d3befa7 WD	169
	170	#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
	171	#define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
	172
	173
716c1dcb WD	174	#define V3_PCI_VENDOR 0x00000000
	175	#define V3_PCI_DEVICE 0x00000002
	176	#define V3_PCI_CMD 0x00000004
	177	#define V3_PCI_STAT 0x00000006
	178	#define V3_PCI_CC_REV 0x00000008
	179	#define V3_PCI_HDR_CF 0x0000000C
	180	#define V3_PCI_IO_BASE 0x00000010
	181	#define V3_PCI_BASE0 0x00000014
	182	#define V3_PCI_BASE1 0x00000018
	183	#define V3_PCI_SUB_VENDOR 0x0000002C
	184	#define V3_PCI_SUB_ID 0x0000002E
	185	#define V3_PCI_ROM 0x00000030
	186	#define V3_PCI_BPARAM 0x0000003C
	187	#define V3_PCI_MAP0 0x00000040
	188	#define V3_PCI_MAP1 0x00000044
	189	#define V3_PCI_INT_STAT 0x00000048
	190	#define V3_PCI_INT_CFG 0x0000004C
	191	#define V3_LB_BASE0 0x00000054
	192	#define V3_LB_BASE1 0x00000058
	193	#define V3_LB_MAP0 0x0000005E
	194	#define V3_LB_MAP1 0x00000062
	195	#define V3_LB_BASE2 0x00000064
	196	#define V3_LB_MAP2 0x00000066
	197	#define V3_LB_SIZE 0x00000068
	198	#define V3_LB_IO_BASE 0x0000006E
	199	#define V3_FIFO_CFG 0x00000070
	200	#define V3_FIFO_PRIORITY 0x00000072
	201	#define V3_FIFO_STAT 0x00000074
	202	#define V3_LB_ISTAT 0x00000076
	203	#define V3_LB_IMASK 0x00000077
	204	#define V3_SYSTEM 0x00000078
	205	#define V3_LB_CFG 0x0000007A
	206	#define V3_PCI_CFG 0x0000007C
	207	#define V3_DMA_PCI_ADR0 0x00000080
	208	#define V3_DMA_PCI_ADR1 0x00000090
	209	#define V3_DMA_LOCAL_ADR0 0x00000084
	210	#define V3_DMA_LOCAL_ADR1 0x00000094
	211	#define V3_DMA_LENGTH0 0x00000088
	212	#define V3_DMA_LENGTH1 0x00000098
	213	#define V3_DMA_CSR0 0x0000008B
	214	#define V3_DMA_CSR1 0x0000009B
	215	#define V3_DMA_CTLB_ADR0 0x0000008C
	216	#define V3_DMA_CTLB_ADR1 0x0000009C
	217	#define V3_DMA_DELAY 0x000000E0
	218	#define V3_MAIL_DATA 0x000000C0
	219	#define V3_PCI_MAIL_IEWR 0x000000D0
	220	#define V3_PCI_MAIL_IERD 0x000000D2
	221	#define V3_LB_MAIL_IEWR 0x000000D4
	222	#define V3_LB_MAIL_IERD 0x000000D6
	223	#define V3_MAIL_WR_STAT 0x000000D8
	224	#define V3_MAIL_RD_STAT 0x000000DA
	225	#define V3_QBA_MAP 0x000000DC
3d3befa7	226
42dfe7a1	227	/* SYSTEM register bits */
716c1dcb WD	228	#define V3_SYSTEM_M_RST_OUT (1 << 15)
716c1dcb WD	229	#define V3_SYSTEM_M_LOCK (1 << 14)
3d3befa7	230
42dfe7a1	231	/* PCI_CFG bits */
716c1dcb WD	232	#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
	233	#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
	234	#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
3d3befa7	235
42dfe7a1	236	/* PCI MAP register bits (PCI -> Local bus) */
716c1dcb WD	237	#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
	238	#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
	239	#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 \| 1 << 10)
	240	#define V3_PCI_MAP_M_SWAP (1 << 9 \| 1 << 8)
	241	#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
	242	#define V3_PCI_MAP_M_REG_EN (1 << 1)
	243	#define V3_PCI_MAP_M_ENABLE (1 << 0)
3d3befa7	244
42dfe7a1	245	/* 9 => 512M window size */
716c1dcb	246	#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
3d3befa7	247
42dfe7a1	248	/* A => 1024M window size */
716c1dcb	249	#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
3d3befa7	250
42dfe7a1	251	/* LB_BASE register bits (Local bus -> PCI) */
716c1dcb WD	252	#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
	253	#define V3_LB_BASE_M_SWAP (1 << 8 \| 1 << 9)
	254	#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
	255	#define V3_LB_BASE_M_PREFETCH (1 << 3)
	256	#define V3_LB_BASE_M_ENABLE (1 << 0)
3d3befa7	257
42dfe7a1	258	/* PCI COMMAND REGISTER bits */
716c1dcb WD	259	#define V3_COMMAND_M_FBB_EN (1 << 9)
	260	#define V3_COMMAND_M_SERR_EN (1 << 8)
	261	#define V3_COMMAND_M_PAR_EN (1 << 6)
	262	#define V3_COMMAND_M_MASTER_EN (1 << 2)
	263	#define V3_COMMAND_M_MEM_EN (1 << 1)
	264	#define V3_COMMAND_M_IO_EN (1 << 0)
3d3befa7 WD	265
	266	#define INTEGRATOR_SC_BASE 0x11000000
	267	#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
	268	#define INTEGRATOR_SC_PCIENABLE \
	269	(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
	270
74f4304e WD	271	/*-----------------------------------------------------------------------
	272	* There are various dependencies on the core module (CM) fitted
	273	* Users should refer to their CM user guide
	274	* - when porting adjust u-boot/Makefile accordingly
	275	* to define the necessary CONFIG_ s for the CM involved
	276	* see e.g. integratorcp_CM926EJ-S_config
	277	*/
	278
	279	#define CM_BASE 0x10000000
	280
	281	/* CM registers common to all integrator/CP CMs */
	282	#define OS_CTRL 0x0000000C
716c1dcb	283	#define CMMASK_REMAP 0x00000005 /* Set remap & led */
74f4304e WD	284	#define CMMASK_RESET 0x00000008
74f4304e WD	285	#define OS_LOCK 0x00000014
716c1dcb WD	286	#define CMVAL_LOCK 0x0000A000 /* Locking value */
716c1dcb WD	287	#define CMMASK_LOCK 0x0000005F /* Locking value */
74f4304e WD	288	#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
	289	#define OS_SDRAM 0x00000020
	290	#define OS_INIT 0x00000024
	291	#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
	292	#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
716c1dcb	293	#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
74f4304e WD	294
	295	#ifdef CONFIG_CM_SPD_DETECT
	296	#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
	297	#endif
3d3befa7	298
0148e8cb	299	#if defined (CONFIG_CM10200E) \|\| defined (CONFIG_CM10220E)
716c1dcb WD	300	#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
	301	* - PLL test clock bypassed
	302	* - bus clock ratio 2
	303	* - little endian
	304	* - vectors at zero
	305	*/
0148e8cb WD	306	#endif /* CM1022xx */
0148e8cb WD	307
716c1dcb	308	#define CMMASK_LE 0x00000008 /* little endian */
0148e8cb	309	#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
716c1dcb WD	310	* - divisor/ratio b00000001
	311	* bx
	312	* - HCLKDIV b000
	313	* bxx
	314	* - PLL BYPASS b00
	315	*/
	316	#endif /* __CONFIG_H */