]>
Commit | Line | Data |
---|---|---|
ab4c62c1 DE |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * Based on include/configs/canyonlands.h | |
6 | * (C) Copyright 2008 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
ab4c62c1 DE |
10 | */ |
11 | ||
12 | /* | |
4c188367 | 13 | * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center |
ab4c62c1 DE |
14 | */ |
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * High Level Configuration Options | |
20 | */ | |
21 | /* | |
4c188367 | 22 | * This config file is used for CompactCenter(codename intip) and DevCon-Center |
ab4c62c1 DE |
23 | */ |
24 | #define CONFIG_460EX 1 /* Specific PPC460EX */ | |
25 | #ifdef CONFIG_DEVCONCENTER | |
26 | #define CONFIG_HOSTNAME devconcenter | |
996d88d8 | 27 | #define CONFIG_IDENT_STRING " devconcenter 0.06" |
ab4c62c1 | 28 | #else |
4c188367 | 29 | #define CONFIG_HOSTNAME intip |
996d88d8 | 30 | #define CONFIG_IDENT_STRING " intip 0.06" |
ab4c62c1 DE |
31 | #endif |
32 | #define CONFIG_440 1 | |
ab4c62c1 | 33 | |
2ae18241 WD |
34 | #ifndef CONFIG_SYS_TEXT_BASE |
35 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
36 | #endif | |
37 | ||
ab4c62c1 DE |
38 | /* |
39 | * Include common defines/options for all AMCC eval boards | |
40 | */ | |
41 | #include "amcc-common.h" | |
42 | ||
43 | #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ | |
44 | ||
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
46 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ | |
47 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
d9f923ff | 48 | #define CONFIG_SYS_GENERIC_BOARD |
ab4c62c1 DE |
49 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
50 | #define CONFIG_FIT | |
51 | #define CFG_ALT_MEMTEST | |
52 | ||
55ac719d DE |
53 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
54 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ | |
55 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
56 | ||
ab4c62c1 DE |
57 | /* |
58 | * Base addresses -- Note these are effective addresses where the | |
59 | * actual resources get mapped (not physical addresses) | |
60 | */ | |
61 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ | |
62 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
63 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE | |
64 | ||
65 | /* EBC stuff */ | |
66 | #ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ | |
67 | #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */ | |
68 | #define CONFIG_SYS_FLASH_SIZE (128 << 20) | |
69 | #else | |
70 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ | |
71 | #define CONFIG_SYS_FLASH_SIZE (64 << 20) | |
72 | #endif | |
73 | ||
74 | #define CONFIG_SYS_NVRAM_BASE 0xE0000000 | |
75 | #define CONFIG_SYS_UART_BASE 0xE0100000 | |
76 | #define CONFIG_SYS_IO_BASE 0xE0200000 | |
77 | ||
78 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ | |
79 | #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 | |
80 | #ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ | |
81 | #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000 | |
82 | #else | |
83 | #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 | |
84 | #endif | |
85 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
86 | (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ | |
87 | | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) | |
88 | ||
89 | #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ | |
90 | #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ | |
bf560807 | 91 | #define CONFIG_SYS_SRAM_SIZE (256 << 10) |
ab4c62c1 DE |
92 | #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 |
93 | ||
ab4c62c1 DE |
94 | #define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ |
95 | ||
96 | /* | |
97 | * Initial RAM & stack pointer (placed in OCM) | |
98 | */ | |
99 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ | |
553f0982 | 100 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
ab4c62c1 | 101 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 102 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
ab4c62c1 DE |
103 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
104 | ||
105 | /* | |
106 | * Serial Port | |
107 | */ | |
550650dd | 108 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
ab4c62c1 DE |
109 | |
110 | /* | |
111 | * Environment | |
112 | */ | |
113 | /* | |
114 | * Define here the location of the environment variables (FLASH). | |
115 | */ | |
116 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
117 | #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ | |
118 | ||
119 | /* | |
120 | * FLASH related | |
121 | */ | |
122 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
123 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
124 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ | |
125 | ||
126 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
127 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
128 | #ifdef CONFIG_DEVCONCENTER | |
129 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/ | |
130 | #else | |
131 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ | |
132 | #endif | |
133 | ||
134 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ | |
135 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ | |
136 | ||
137 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */ | |
138 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ | |
139 | ||
140 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
141 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ | |
142 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
143 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
144 | ||
145 | /* Address and size of Redundant Environment Sector */ | |
146 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) | |
147 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
148 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
149 | ||
150 | /* | |
151 | * DDR SDRAM | |
152 | */ | |
153 | ||
154 | #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ | |
155 | ||
156 | #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ | |
157 | #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ | |
158 | #undef CONFIG_PPC4xx_DDR_METHOD_A | |
159 | ||
160 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
161 | /* Memory Queue */ | |
162 | #define CONFIG_SYS_SDRAM_R0BAS 0x0000f800 | |
163 | #define CONFIG_SYS_SDRAM_R1BAS 0x00000000 | |
164 | #define CONFIG_SYS_SDRAM_R2BAS 0x00000000 | |
165 | #define CONFIG_SYS_SDRAM_R3BAS 0x00000000 | |
166 | #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 | |
167 | #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 | |
91d59904 | 168 | #define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 |
ab4c62c1 DE |
169 | #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 |
170 | #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 | |
171 | ||
172 | /* SDRAM Controller */ | |
173 | #define CONFIG_SYS_SDRAM0_MB0CF 0x00000201 | |
174 | #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 | |
175 | #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 | |
176 | #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 | |
91d59904 | 177 | #define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000 |
ab4c62c1 DE |
178 | #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 |
179 | #define CONFIG_SYS_SDRAM0_MODT0 0x00000000 | |
180 | #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 | |
181 | #define CONFIG_SYS_SDRAM0_MODT2 0x00000000 | |
182 | #define CONFIG_SYS_SDRAM0_MODT3 0x00000000 | |
183 | #define CONFIG_SYS_SDRAM0_CODT 0x00000020 | |
184 | #define CONFIG_SYS_SDRAM0_RTR 0x06180000 | |
185 | #define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000 | |
186 | #define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 | |
187 | #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 | |
188 | #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 | |
91d59904 | 189 | #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 |
15cc385e | 190 | #define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552 |
ab4c62c1 DE |
191 | #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 |
192 | #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 | |
193 | #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 | |
194 | #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 | |
195 | #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 | |
15cc385e | 196 | #define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452 |
91d59904 DE |
197 | #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 |
198 | #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 | |
ab4c62c1 DE |
199 | #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 |
200 | #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 | |
201 | #define CONFIG_SYS_SDRAM0_RQDC 0x80000038 | |
91d59904 DE |
202 | #define CONFIG_SYS_SDRAM0_RFDC 0x00000257 |
203 | #define CONFIG_SYS_SDRAM0_RDCC 0x40000000 | |
ab4c62c1 DE |
204 | #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 |
205 | #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 | |
15cc385e | 206 | #define CONFIG_SYS_SDRAM0_WRDTR 0x86000823 |
ab4c62c1 DE |
207 | #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 |
208 | #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 | |
91d59904 | 209 | #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 |
15cc385e | 210 | #define CONFIG_SYS_SDRAM0_MMODE 0x00000452 |
91d59904 | 211 | #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 |
ab4c62c1 DE |
212 | |
213 | #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ | |
214 | ||
215 | /* | |
216 | * I2C | |
217 | */ | |
880540de | 218 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
ab4c62c1 DE |
219 | |
220 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
221 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
222 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
223 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
224 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
225 | ||
226 | /* I2C bootstrap EEPROM */ | |
227 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 | |
228 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
229 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
230 | ||
231 | /* I2C SYSMON */ | |
232 | #define CONFIG_DTT_LM63 1 /* National LM63 */ | |
233 | #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ | |
234 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ | |
235 | { { 40, 10 }, { 50, 20 }, { 60, 40 } } | |
236 | #define CONFIG_DTT_TACH_LIMIT 0xa10 | |
237 | ||
238 | /* RTC configuration */ | |
239 | #define CONFIG_RTC_DS1337 1 | |
240 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
241 | ||
242 | /* | |
243 | * Ethernet | |
244 | */ | |
245 | #define CONFIG_IBM_EMAC4_V4 1 | |
246 | ||
247 | #define CONFIG_HAS_ETH0 | |
248 | #define CONFIG_HAS_ETH1 | |
249 | ||
250 | #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ | |
251 | #define CONFIG_PHY1_ADDR 3 | |
252 | ||
253 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
254 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
255 | #define CONFIG_PHY_DYNAMIC_ANEG 1 | |
256 | ||
257 | /* | |
258 | * USB-OHCI | |
259 | */ | |
260 | #define CONFIG_USB_OHCI_NEW | |
261 | #define CONFIG_USB_STORAGE | |
262 | #undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/ | |
263 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ | |
264 | #define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ | |
265 | #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) | |
266 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
267 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
268 | ||
269 | /* | |
270 | * Default environment variables | |
271 | */ | |
272 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
273 | CONFIG_AMCC_DEF_ENV \ | |
274 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
275 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
276 | "kernel_addr=fc000000\0" \ | |
277 | "fdt_addr=fc1e0000\0" \ | |
278 | "ramdisk_addr=fc200000\0" \ | |
279 | "pciconfighost=1\0" \ | |
280 | "pcie_mode=RP:RP\0" \ | |
281 | "" | |
282 | ||
283 | /* | |
284 | * Commands additional to the ones defined in amcc-common.h | |
285 | */ | |
286 | #define CONFIG_CMD_CHIP_CONFIG | |
287 | #define CONFIG_CMD_DATE | |
288 | #define CONFIG_CMD_DTT | |
289 | #define CONFIG_CMD_EXT2 | |
290 | #define CONFIG_CMD_FAT | |
291 | #define CONFIG_CMD_PCI | |
292 | #define CONFIG_CMD_SDRAM | |
293 | #define CONFIG_CMD_SNTP | |
294 | #define CONFIG_CMD_USB | |
295 | ||
296 | /* Partitions */ | |
297 | #define CONFIG_MAC_PARTITION | |
298 | #define CONFIG_DOS_PARTITION | |
299 | #define CONFIG_ISO_PARTITION | |
300 | ||
301 | /* | |
302 | * PCI stuff | |
303 | */ | |
304 | /* General PCI */ | |
305 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 306 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
ab4c62c1 DE |
307 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
308 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
309 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
310 | #define CONFIG_PCI_DISABLE_PCIE | |
311 | ||
312 | /* Board-specific PCI */ | |
313 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ | |
314 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
315 | ||
316 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
317 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
318 | ||
319 | ||
320 | /* | |
321 | * External Bus Controller (EBC) Setup | |
322 | */ | |
323 | ||
324 | /* | |
325 | * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the | |
326 | * boot EBC mapping only supports a maximum of 16MBytes | |
327 | * (4.ff00.0000 - 4.ffff.ffff). | |
328 | * To solve this problem, the FLASH has to get remapped to another | |
329 | * EBC address which accepts bigger regions: | |
330 | * | |
331 | * 0xfc00.0000 -> 4.cc00.0000 | |
332 | */ | |
333 | ||
334 | ||
335 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
336 | #define CONFIG_SYS_EBC_PB0AP 0x10055e00 | |
337 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) | |
338 | ||
339 | /* Memory Bank 1 (NVRAM) initialization */ | |
340 | #define CONFIG_SYS_EBC_PB1AP 0x02815480 | |
341 | /* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/ | |
342 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000) | |
343 | ||
344 | /* Memory Bank 2 (UART) initialization */ | |
345 | #define CONFIG_SYS_EBC_PB2AP 0x02815480 | |
346 | /* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/ | |
347 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000) | |
348 | ||
349 | /* Memory Bank 3 (IO) initialization */ | |
350 | #define CONFIG_SYS_EBC_PB3AP 0x02815480 | |
351 | /* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/ | |
352 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000) | |
353 | ||
354 | /* | |
355 | * PPC4xx GPIO Configuration | |
356 | */ | |
357 | /* 460EX: Use USB configuration */ | |
358 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ | |
359 | { \ | |
360 | /* GPIO Core 0 */ \ | |
361 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ | |
362 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ | |
363 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ | |
364 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ | |
365 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ | |
366 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ | |
367 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ | |
368 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ | |
369 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ | |
370 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ | |
371 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ | |
372 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ | |
373 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ | |
374 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ | |
375 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ | |
376 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ | |
377 | {GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ | |
378 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ | |
379 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ | |
380 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ | |
381 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ | |
382 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ | |
383 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ | |
384 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ | |
385 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ | |
386 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ | |
387 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ | |
388 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ | |
389 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ | |
390 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ | |
391 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ | |
392 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ | |
393 | }, \ | |
394 | { \ | |
395 | /* GPIO Core 1 */ \ | |
396 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ | |
397 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ | |
398 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
399 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
400 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ | |
401 | {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ | |
402 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
403 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
404 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ | |
405 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ | |
406 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ | |
407 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ | |
408 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ | |
409 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ | |
410 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ | |
411 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ | |
412 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ | |
413 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
414 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \ | |
415 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \ | |
416 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \ | |
417 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \ | |
418 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \ | |
419 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \ | |
420 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \ | |
421 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
422 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
423 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
424 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
425 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \ | |
426 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \ | |
427 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \ | |
428 | } \ | |
429 | } | |
430 | ||
431 | #endif /* __CONFIG_H */ |