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a605ea7e DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a605ea7e DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ | |
a605ea7e DE |
12 | #define CONFIG_IO 1 /* on a Io board */ |
13 | ||
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
15 | ||
16 | /* | |
17 | * Include common defines/options for all AMCC eval boards | |
18 | */ | |
19 | #define CONFIG_HOSTNAME io | |
28437154 | 20 | #define CONFIG_IDENT_STRING " io 0.06" |
a605ea7e DE |
21 | #include "amcc-common.h" |
22 | ||
6e9e6c36 DE |
23 | #define CONFIG_BOARD_EARLY_INIT_F |
24 | #define CONFIG_BOARD_EARLY_INIT_R | |
b19bf834 | 25 | #define CONFIG_MISC_INIT_R |
6e9e6c36 | 26 | #define CONFIG_LAST_STAGE_INIT |
a605ea7e DE |
27 | |
28 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
29 | ||
30 | /* | |
31 | * Configure PLL | |
32 | */ | |
33 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 | |
34 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 | |
35 | ||
996d88d8 | 36 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
996d88d8 | 37 | |
a605ea7e | 38 | /* new uImage format support */ |
9a4f479b | 39 | #define CONFIG_FIT_DISABLE_SHA256 |
a605ea7e DE |
40 | |
41 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
42 | ||
43 | /* | |
44 | * Default environment variables | |
45 | */ | |
46 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
47 | CONFIG_AMCC_DEF_ENV \ | |
48 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
49 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
50 | "kernel_addr=fc000000\0" \ | |
51 | "fdt_addr=fc1e0000\0" \ | |
52 | "ramdisk_addr=fc200000\0" \ | |
53 | "" | |
54 | ||
55 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
56 | #define CONFIG_HAS_ETH0 | |
57 | #define CONFIG_HAS_ETH1 | |
58 | #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ | |
59 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
60 | ||
61 | /* | |
62 | * Commands additional to the ones defined in amcc-common.h | |
63 | */ | |
b19bf834 | 64 | #define CONFIG_CMD_DTT |
4fb9b41b DE |
65 | #undef CONFIG_CMD_DHCP |
66 | #undef CONFIG_CMD_DIAG | |
a605ea7e | 67 | #undef CONFIG_CMD_EEPROM |
4fb9b41b DE |
68 | #undef CONFIG_CMD_I2C |
69 | #undef CONFIG_CMD_IRQ | |
a605ea7e DE |
70 | |
71 | /* | |
72 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
73 | */ | |
74 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
75 | ||
76 | /* SDRAM timings used in datasheet */ | |
77 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
78 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
79 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ | |
80 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
81 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
82 | ||
83 | /* | |
84 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
85 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
86 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. | |
87 | * The Linux BASE_BAUD define should match this configuration. | |
88 | * baseBaud = cpuClock/(uartDivisor*16) | |
89 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
90 | * set Linux BASE_BAUD to 403200. | |
91 | */ | |
92 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
93 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ | |
94 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
95 | #define CONFIG_SYS_BASE_BAUD 691200 | |
96 | ||
97 | /* | |
98 | * I2C stuff | |
99 | */ | |
880540de | 100 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
a605ea7e DE |
101 | |
102 | /* Temp sensor/hwmon/dtt */ | |
103 | #define CONFIG_DTT_LM63 1 /* National LM63 */ | |
104 | #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ | |
105 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ | |
106 | { { 40, 10 }, { 50, 20 }, { 60, 40 } } | |
107 | #define CONFIG_DTT_TACH_LIMIT 0xa10 | |
108 | ||
109 | /* | |
110 | * FLASH organization | |
111 | */ | |
112 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
113 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
114 | ||
115 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
116 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
117 | ||
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
119 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ | |
120 | ||
121 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ | |
122 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ | |
123 | ||
124 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ | |
a605ea7e DE |
125 | |
126 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ | |
127 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ | |
128 | ||
129 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
130 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
131 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) | |
132 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
133 | ||
134 | /* Address and size of Redundant Environment Sector */ | |
135 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
136 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
137 | #endif | |
138 | ||
139 | /* Gbit PHYs */ | |
140 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
141 | #define CONFIG_BITBANGMII_MULTI | |
142 | ||
143 | #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */ | |
144 | #define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */ | |
145 | ||
146 | #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy" | |
147 | ||
148 | /* | |
149 | * PPC405 GPIO Configuration | |
150 | */ | |
151 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ | |
152 | { \ | |
153 | /* GPIO Core 0 */ \ | |
154 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
155 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
156 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
157 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
158 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
159 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
160 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
161 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ | |
162 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
163 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
164 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
165 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
166 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
167 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
168 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
169 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
170 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
171 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
172 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
173 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
174 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
175 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
176 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
177 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
178 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
179 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
180 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
181 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
182 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
183 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
184 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
185 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
186 | } \ | |
187 | } | |
188 | ||
189 | /* | |
190 | * Definitions for initial stack pointer and data area (in data cache) | |
191 | */ | |
192 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
193 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
194 | ||
195 | /* On Chip Memory location */ | |
196 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
197 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
198 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ | |
199 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ | |
200 | ||
a605ea7e | 201 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
627b73e2 | 202 | (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) |
a605ea7e DE |
203 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
204 | ||
205 | /* | |
206 | * External Bus Controller (EBC) Setup | |
207 | */ | |
208 | ||
209 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
210 | #define CONFIG_SYS_EBC_PB0AP 0xa382a880 | |
211 | /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ | |
212 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 | |
213 | ||
214 | /* Memory Bank 1 (NVRAM) initializatio */ | |
215 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 | |
216 | /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ | |
217 | #define CONFIG_SYS_EBC_PB1CR 0x7f318000 | |
218 | ||
219 | /* Memory Bank 2 (FPGA) initialization */ | |
2da0fc0d | 220 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 |
a605ea7e DE |
221 | #define CONFIG_SYS_EBC_PB2AP 0x02025080 |
222 | /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ | |
223 | #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 | |
224 | ||
2da0fc0d DE |
225 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
226 | #define CONFIG_SYS_FPGA_DONE(k) 0x0010 | |
227 | ||
228 | #define CONFIG_SYS_FPGA_COUNT 1 | |
a605ea7e | 229 | |
aba27acf DE |
230 | #define CONFIG_SYS_FPGA_PTR \ |
231 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } | |
232 | ||
233 | #define CONFIG_SYS_FPGA_COMMON | |
234 | ||
a605ea7e DE |
235 | /* Memory Bank 3 (Latches) initialization */ |
236 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 | |
237 | #define CONFIG_SYS_EBC_PB3AP 0xa2015480 | |
238 | /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ | |
239 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 | |
240 | ||
241 | #define CONFIG_SYS_LATCH0_RESET 0xffff | |
242 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
243 | #define CONFIG_SYS_LATCH1_RESET 0xffbf | |
244 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
245 | ||
246 | #endif /* __CONFIG_H */ |