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255ef4d9 DE |
1 | /* |
2 | * (C) Copyright 2011 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * based on kilauea.h | |
6 | * by Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * and Grant Erickson <gerickson@nuovations.com> | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
255ef4d9 DE |
10 | */ |
11 | ||
12 | /************************************************************************ | |
13 | * io64.h - configuration for Guntermann & Drunck Io64 (405EX) | |
14 | ***********************************************************************/ | |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
19 | /*----------------------------------------------------------------------- | |
20 | * High Level Configuration Options | |
21 | *----------------------------------------------------------------------*/ | |
22 | #define CONFIG_IO64 1 /* Board is Io64 */ | |
255ef4d9 DE |
23 | #define CONFIG_405EX 1 /* Specifc 405EX support*/ |
24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ | |
25 | ||
26 | #ifndef CONFIG_SYS_TEXT_BASE | |
27 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
28 | #endif | |
29 | ||
30 | /* | |
31 | * CHIP_21 errata | |
32 | */ | |
33 | #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY | |
34 | ||
35 | /* | |
36 | * Include common defines/options for all AMCC eval boards | |
37 | */ | |
38 | #define CONFIG_HOSTNAME io64 | |
996d88d8 | 39 | #define CONFIG_IDENT_STRING " io64 0.02" |
255ef4d9 DE |
40 | #include "amcc-common.h" |
41 | ||
42 | #define CONFIG_BOARD_EARLY_INIT_F | |
43 | #define CONFIG_BOARD_EARLY_INIT_R | |
44 | #define CONFIG_MISC_INIT_R | |
45 | #define CONFIG_LAST_STAGE_INIT | |
d9f923ff | 46 | #define CONFIG_SYS_GENERIC_BOARD |
255ef4d9 DE |
47 | |
48 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ | |
49 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ | |
50 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
51 | ||
52 | /* new uImage format support */ | |
53 | #define CONFIG_FIT | |
54 | #define CONFIG_FIT_VERBOSE | |
55 | ||
56 | /*----------------------------------------------------------------------- | |
57 | * Base addresses -- Note these are effective addresses where the | |
58 | * actual resources get mapped (not physical addresses) | |
59 | *----------------------------------------------------------------------*/ | |
60 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
61 | #define CONFIG_SYS_NVRAM_BASE 0xF0000000 | |
62 | #define CONFIG_SYS_FPGA0_BASE 0xF0100000 | |
63 | #define CONFIG_SYS_FPGA1_BASE 0xF0108000 | |
64 | #define CONFIG_SYS_LATCH_BASE 0xF0200000 | |
65 | ||
66 | /*----------------------------------------------------------------------- | |
67 | * Initial RAM & Stack Pointer Configuration Options | |
68 | * | |
69 | * There are traditionally three options for the primordial | |
70 | * (i.e. initial) stack usage on the 405-series: | |
71 | * | |
72 | * 1) On-chip Memory (OCM) (i.e. SRAM) | |
73 | * 2) Data cache | |
74 | * 3) SDRAM | |
75 | * | |
76 | * For the 405EX(r), there is no OCM, so we are left with (2) or (3) | |
77 | * the latter of which is less than desireable since it requires | |
78 | * setting up the SDRAM and ECC in assembly code. | |
79 | * | |
80 | * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip | |
81 | * select on the External Bus Controller (EBC) and then select a | |
82 | * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, | |
83 | * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and | |
84 | * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, | |
85 | * physical SDRAM to use (3). | |
86 | *-----------------------------------------------------------------------*/ | |
87 | ||
88 | #define CONFIG_SYS_INIT_DCACHE_CS 4 | |
89 | ||
90 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) | |
91 | #define CONFIG_SYS_INIT_RAM_ADDR \ | |
92 | (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ | |
93 | #else | |
94 | #define CONFIG_SYS_INIT_RAM_ADDR \ | |
95 | (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ | |
96 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
97 | ||
98 | #define CONFIG_SYS_INIT_RAM_SIZE \ | |
99 | (4 << 10) /* 4 KiB */ | |
100 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
101 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
102 | ||
103 | /* | |
104 | * If the data cache is being used for the primordial stack and global | |
105 | * data area, the POST word must be placed somewhere else. The General | |
106 | * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves | |
107 | * its compare and mask register contents across reset, so it is used | |
108 | * for the POST word. | |
109 | */ | |
110 | ||
111 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) | |
112 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
113 | # define CONFIG_SYS_POST_WORD_ADDR \ | |
114 | (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) | |
115 | #else | |
116 | # define CONFIG_SYS_INIT_EXTRA_SIZE 16 | |
117 | # define CONFIG_SYS_INIT_SP_OFFSET \ | |
118 | (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) | |
119 | # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR | |
120 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
121 | ||
122 | /*----------------------------------------------------------------------- | |
123 | * Serial Port | |
124 | *----------------------------------------------------------------------*/ | |
125 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
126 | #define CONFIG_SYS_BASE_BAUD 691200 | |
127 | ||
128 | /*----------------------------------------------------------------------- | |
129 | * Environment | |
130 | *----------------------------------------------------------------------*/ | |
131 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
132 | ||
133 | /*----------------------------------------------------------------------- | |
134 | * FLASH related | |
135 | *----------------------------------------------------------------------*/ | |
136 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
137 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
138 | ||
139 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
140 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
141 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
142 | ||
143 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
144 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
145 | ||
146 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
147 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
148 | ||
149 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
150 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
151 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) | |
152 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
153 | ||
154 | /* Address and size of Redundant Environment Sector */ | |
155 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
156 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
157 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
158 | ||
159 | /* Gbit PHYs */ | |
160 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
161 | #define CONFIG_BITBANGMII_MULTI | |
162 | ||
163 | #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */ | |
164 | #define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */ | |
165 | ||
166 | #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0" | |
167 | ||
168 | #define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */ | |
169 | #define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */ | |
170 | ||
171 | #define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1" | |
172 | ||
173 | /*----------------------------------------------------------------------- | |
174 | * DDR SDRAM | |
175 | *----------------------------------------------------------------------*/ | |
176 | #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */ | |
177 | ||
178 | /* | |
179 | * CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
180 | * | |
181 | * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx | |
182 | * SDRAM Controller DDR autocalibration values and takes a lot longer | |
183 | * to run than Method_B. | |
184 | * (See the Method_A and Method_B algorithm discription in the file: | |
185 | * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) | |
186 | * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A | |
187 | * | |
188 | * DDR Autocalibration Method_B is the default. | |
189 | */ | |
190 | #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
191 | #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION | |
192 | #undef CONFIG_PPC4xx_DDR_METHOD_A | |
193 | ||
194 | #define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE) | |
195 | ||
196 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
197 | #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ | |
198 | SDRAM_RXBAS_SDSZ_128MB | \ | |
199 | SDRAM_RXBAS_SDAM_MODE2 | \ | |
200 | SDRAM_RXBAS_SDBE_ENABLE) | |
201 | #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE | |
202 | #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE | |
203 | #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE | |
204 | #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ | |
205 | SDRAM_MCOPT1_4_BANKS | \ | |
206 | SDRAM_MCOPT1_DDR2_TYPE | \ | |
207 | SDRAM_MCOPT1_QDEP | \ | |
208 | SDRAM_MCOPT1_DCOO_DISABLED) | |
209 | #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 | |
210 | #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ | |
211 | SDRAM_MODT_EB0R_ENABLE) | |
212 | #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 | |
213 | #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ | |
214 | SDRAM_CODT_CKLZ_36OHM | \ | |
215 | SDRAM_CODT_DQS_1_8_V_DDR2 | \ | |
216 | SDRAM_CODT_IO_NMODE) | |
217 | #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) | |
218 | #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ | |
219 | SDRAM_INITPLR_IMWT_ENCODE(80) | \ | |
220 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) | |
221 | #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ | |
222 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ | |
223 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
224 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
225 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
226 | #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ | |
227 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
228 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
229 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ | |
230 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) | |
231 | #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ | |
232 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
233 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
234 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ | |
235 | SDRAM_INITPLR_IMA_ENCODE(0)) | |
236 | #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ | |
237 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
238 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
239 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
240 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ | |
241 | JEDEC_MA_EMR_RTT_75OHM)) | |
242 | #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ | |
243 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
244 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
245 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
246 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
247 | JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ | |
248 | JEDEC_MA_MR_BLEN_4 | \ | |
249 | JEDEC_MA_MR_DLL_RESET)) | |
250 | #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ | |
251 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ | |
252 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
253 | SDRAM_INITPLR_IBA_ENCODE(0x0) | \ | |
254 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
255 | #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ | |
256 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
257 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
258 | #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ | |
259 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
260 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
261 | #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ | |
262 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
263 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
264 | #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ | |
265 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
266 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
267 | #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ | |
268 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
269 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
270 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
271 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
272 | JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ | |
273 | JEDEC_MA_MR_BLEN_4)) | |
274 | #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ | |
275 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
276 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
277 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
278 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ | |
279 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
280 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
281 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
282 | JEDEC_MA_EMR_ODS_NORMAL)) | |
283 | #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ | |
284 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
285 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
286 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
287 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ | |
288 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
289 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
290 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
291 | JEDEC_MA_EMR_ODS_NORMAL)) | |
292 | #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) | |
293 | #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) | |
294 | #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ | |
295 | SDRAM_RQDC_RQFD_ENCODE(56)) | |
296 | #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) | |
297 | #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) | |
298 | #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ | |
299 | SDRAM_DLCR_DLCS_CONT_DONE | \ | |
300 | SDRAM_DLCR_DLCV_ENCODE(165)) | |
301 | #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) | |
302 | #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 | |
303 | #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ | |
304 | SDRAM_SDTR1_RTW_2_CLK | \ | |
305 | SDRAM_SDTR1_WTWO_1_CLK | \ | |
306 | SDRAM_SDTR1_RTRO_1_CLK) | |
307 | #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ | |
308 | SDRAM_SDTR2_WTR_2_CLK | \ | |
309 | SDRAM_SDTR2_XSNR_32_CLK | \ | |
310 | SDRAM_SDTR2_WPC_4_CLK | \ | |
311 | SDRAM_SDTR2_RPC_2_CLK | \ | |
312 | SDRAM_SDTR2_RP_3_CLK | \ | |
313 | SDRAM_SDTR2_RRD_2_CLK) | |
314 | #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \ | |
315 | SDRAM_SDTR3_RC_ENCODE(12) | \ | |
316 | SDRAM_SDTR3_XCS | \ | |
317 | SDRAM_SDTR3_RFC_ENCODE(21)) | |
318 | #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ | |
319 | SDRAM_MMODE_DCL_DDR2_5_0_CLK | \ | |
320 | SDRAM_MMODE_BLEN_4) | |
321 | #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ | |
322 | SDRAM_MEMODE_RTT_75OHM) | |
323 | ||
324 | /*----------------------------------------------------------------------- | |
325 | * I2C | |
326 | *----------------------------------------------------------------------*/ | |
880540de | 327 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
255ef4d9 DE |
328 | |
329 | #define CONFIG_PCA9698 1 /* NXP PCA9698 */ | |
330 | ||
331 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ | |
332 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
333 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
334 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
335 | ||
336 | /* I2C bootstrap EEPROM */ | |
337 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 | |
338 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
339 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
340 | ||
341 | /* Temp sensor/hwmon/dtt */ | |
342 | #define CONFIG_DTT_LM63 1 /* National LM63 */ | |
343 | #define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ | |
344 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ | |
345 | { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ | |
346 | { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } | |
347 | #define CONFIG_DTT_TACH_LIMIT 0xa10 | |
348 | ||
349 | /*----------------------------------------------------------------------- | |
350 | * Ethernet | |
351 | *----------------------------------------------------------------------*/ | |
352 | #define CONFIG_M88E1111_PHY 1 | |
353 | #define CONFIG_IBM_EMAC4_V4 1 | |
354 | #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII | |
355 | #define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */ | |
356 | ||
357 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
358 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
359 | ||
360 | #define CONFIG_HAS_ETH0 1 | |
361 | ||
362 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
363 | #define CONFIG_PHY1_ADDR 0x13 | |
364 | ||
365 | /* Debug messages for the DDR autocalibration */ | |
366 | #define CONFIG_AUTOCALIB "silent\0" | |
367 | ||
368 | /* | |
369 | * Default environment variables | |
370 | */ | |
371 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
372 | CONFIG_AMCC_DEF_ENV \ | |
373 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
374 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
375 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
376 | "logversion=2\0" \ | |
377 | "kernel_addr=fc000000\0" \ | |
378 | "fdt_addr=fc1e0000\0" \ | |
379 | "ramdisk_addr=fc200000\0" \ | |
380 | "pciconfighost=1\0" \ | |
381 | "pcie_mode=RP:RP\0" \ | |
382 | "" | |
383 | ||
384 | /* | |
385 | * Commands additional to the ones defined in amcc-common.h | |
386 | */ | |
387 | #define CONFIG_CMD_CHIP_CONFIG | |
388 | #define CONFIG_CMD_DTT | |
389 | ||
390 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
391 | ||
392 | /* POST support */ | |
393 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ | |
394 | CONFIG_SYS_POST_CPU | \ | |
395 | CONFIG_SYS_POST_ETHER | \ | |
396 | CONFIG_SYS_POST_I2C | \ | |
397 | CONFIG_SYS_POST_MEMORY_ON | \ | |
398 | CONFIG_SYS_POST_UART) | |
399 | ||
400 | /* Define here the base-addresses of the UARTs to test in POST */ | |
401 | #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ | |
402 | CONFIG_SYS_NS16550_COM2 } | |
403 | ||
404 | #define CONFIG_LOGBUFFER | |
405 | #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ | |
406 | ||
407 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
408 | ||
409 | /*----------------------------------------------------------------------- | |
410 | * External Bus Controller (EBC) Setup | |
411 | *----------------------------------------------------------------------*/ | |
412 | ||
413 | /* Memory Bank 0 (NOR-flash) */ | |
414 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
415 | EBC_BXAP_TWT_ENCODE(11) | \ | |
416 | EBC_BXAP_BCE_DISABLE | \ | |
417 | EBC_BXAP_BCT_2TRANS | \ | |
418 | EBC_BXAP_CSN_ENCODE(0) | \ | |
419 | EBC_BXAP_OEN_ENCODE(0) | \ | |
420 | EBC_BXAP_WBN_ENCODE(1) | \ | |
421 | EBC_BXAP_WBF_ENCODE(2) | \ | |
422 | EBC_BXAP_TH_ENCODE(2) | \ | |
423 | EBC_BXAP_RE_DISABLED | \ | |
424 | EBC_BXAP_SOR_NONDELAYED | \ | |
425 | EBC_BXAP_BEM_WRITEONLY | \ | |
426 | EBC_BXAP_PEN_DISABLED) | |
427 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ | |
428 | EBC_BXCR_BS_64MB | \ | |
429 | EBC_BXCR_BU_RW | \ | |
430 | EBC_BXCR_BW_16BIT) | |
431 | ||
432 | /* Memory Bank 1 (NVRAM/Uart) */ | |
433 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \ | |
434 | EBC_BXAP_FWT_ENCODE(8) | \ | |
435 | EBC_BXAP_BWT_ENCODE(4) | \ | |
436 | EBC_BXAP_BCE_DISABLE | \ | |
437 | EBC_BXAP_BCT_2TRANS | \ | |
438 | EBC_BXAP_CSN_ENCODE(0) | \ | |
439 | EBC_BXAP_OEN_ENCODE(1) | \ | |
440 | EBC_BXAP_WBN_ENCODE(1) | \ | |
441 | EBC_BXAP_WBF_ENCODE(1) | \ | |
442 | EBC_BXAP_TH_ENCODE(2) | \ | |
443 | EBC_BXAP_RE_DISABLED | \ | |
444 | EBC_BXAP_SOR_NONDELAYED | \ | |
445 | EBC_BXAP_BEM_WRITEONLY | \ | |
446 | EBC_BXAP_PEN_DISABLED) | |
447 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \ | |
448 | EBC_BXCR_BS_1MB | \ | |
449 | EBC_BXCR_BU_RW | \ | |
450 | EBC_BXCR_BW_8BIT) | |
451 | ||
452 | /* Memory Bank 2 (FPGA) */ | |
453 | #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ | |
454 | EBC_BXAP_TWT_ENCODE(5) | \ | |
455 | EBC_BXAP_BCE_DISABLE | \ | |
456 | EBC_BXAP_BCT_2TRANS | \ | |
457 | EBC_BXAP_CSN_ENCODE(0) | \ | |
458 | EBC_BXAP_OEN_ENCODE(2) | \ | |
459 | EBC_BXAP_WBN_ENCODE(1) | \ | |
460 | EBC_BXAP_WBF_ENCODE(1) | \ | |
461 | EBC_BXAP_TH_ENCODE(0) | \ | |
462 | EBC_BXAP_RE_DISABLED | \ | |
463 | EBC_BXAP_SOR_NONDELAYED | \ | |
464 | EBC_BXAP_BEM_WRITEONLY | \ | |
465 | EBC_BXAP_PEN_DISABLED) | |
466 | #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ | |
467 | EBC_BXCR_BS_1MB | \ | |
468 | EBC_BXCR_BU_RW | \ | |
469 | EBC_BXCR_BW_16BIT) | |
470 | ||
471 | /* Memory Bank 3 (Latches) */ | |
472 | #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ | |
473 | EBC_BXAP_FWT_ENCODE(8) | \ | |
474 | EBC_BXAP_BWT_ENCODE(4) | \ | |
475 | EBC_BXAP_BCE_DISABLE | \ | |
476 | EBC_BXAP_BCT_2TRANS | \ | |
477 | EBC_BXAP_CSN_ENCODE(0) | \ | |
478 | EBC_BXAP_OEN_ENCODE(1) | \ | |
479 | EBC_BXAP_WBN_ENCODE(1) | \ | |
480 | EBC_BXAP_WBF_ENCODE(1) | \ | |
481 | EBC_BXAP_TH_ENCODE(2) | \ | |
482 | EBC_BXAP_RE_DISABLED | \ | |
483 | EBC_BXAP_SOR_NONDELAYED | \ | |
484 | EBC_BXAP_BEM_WRITEONLY | \ | |
485 | EBC_BXAP_PEN_DISABLED) | |
486 | #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ | |
487 | EBC_BXCR_BS_1MB | \ | |
488 | EBC_BXCR_BU_RW | \ | |
489 | EBC_BXCR_BW_16BIT) | |
490 | ||
491 | /* EBC peripherals */ | |
492 | ||
493 | #define CONFIG_SYS_FPGA_BASE(k) \ | |
494 | (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) | |
495 | ||
496 | #define CONFIG_SYS_FPGA_DONE(k) \ | |
497 | (k ? 0x0040 : 0x0080) | |
498 | ||
499 | #define CONFIG_SYS_FPGA_COUNT 2 | |
500 | ||
aba27acf DE |
501 | #define CONFIG_SYS_FPGA_PTR { \ |
502 | (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ | |
503 | (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } | |
504 | ||
505 | #define CONFIG_SYS_FPGA_COMMON | |
506 | ||
255ef4d9 DE |
507 | #define CONFIG_SYS_LATCH0_RESET 0xffff |
508 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
509 | #define CONFIG_SYS_LATCH1_RESET 0xffbf | |
510 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
511 | ||
512 | /*----------------------------------------------------------------------- | |
513 | * GPIO Setup | |
514 | *----------------------------------------------------------------------*/ | |
515 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \ | |
516 | { \ | |
517 | /* GPIO Core 0 */ \ | |
518 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \ | |
519 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \ | |
520 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \ | |
521 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \ | |
522 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \ | |
523 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \ | |
524 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \ | |
525 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \ | |
526 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \ | |
527 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \ | |
528 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \ | |
529 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \ | |
530 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \ | |
531 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \ | |
532 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \ | |
533 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \ | |
534 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \ | |
535 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \ | |
536 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \ | |
537 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \ | |
538 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \ | |
539 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \ | |
540 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \ | |
541 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \ | |
542 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \ | |
543 | {GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \ | |
544 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \ | |
545 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \ | |
546 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \ | |
547 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \ | |
548 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \ | |
549 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \ | |
550 | } \ | |
551 | } | |
552 | ||
553 | #define CONFIG_SYS_GPIO_STARTUP_FINISHED 15 | |
554 | #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14 | |
555 | ||
556 | #endif /* __CONFIG_H */ |