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a605ea7e DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a605ea7e DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ | |
a605ea7e DE |
12 | #define CONFIG_IOCON 1 /* on a IoCon board */ |
13 | ||
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
15 | ||
16 | /* | |
17 | * Include common defines/options for all AMCC eval boards | |
18 | */ | |
19 | #define CONFIG_HOSTNAME iocon | |
a605ea7e DE |
20 | #include "amcc-common.h" |
21 | ||
57e5ecaf TR |
22 | /* Reclaim some space. */ |
23 | #undef CONFIG_SYS_LONGHELP | |
24 | ||
6e9e6c36 | 25 | #define CONFIG_BOARD_EARLY_INIT_R |
a605ea7e DE |
26 | #define CONFIG_LAST_STAGE_INIT |
27 | ||
28 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
29 | ||
30 | /* | |
31 | * Configure PLL | |
32 | */ | |
33 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 | |
34 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 | |
35 | ||
a605ea7e DE |
36 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
37 | ||
38 | /* | |
39 | * Default environment variables | |
40 | */ | |
41 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
42 | CONFIG_AMCC_DEF_ENV \ | |
43 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
44 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
45 | "kernel_addr=fc000000\0" \ | |
46 | "fdt_addr=fc1e0000\0" \ | |
47 | "ramdisk_addr=fc200000\0" \ | |
48 | "" | |
49 | ||
50 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
51 | #define CONFIG_HAS_ETH0 | |
52 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
53 | ||
54 | /* | |
55 | * Commands additional to the ones defined in amcc-common.h | |
56 | */ | |
4fb9b41b | 57 | #undef CONFIG_CMD_IRQ |
a605ea7e DE |
58 | |
59 | /* | |
60 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
61 | */ | |
62 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
63 | ||
64 | /* SDRAM timings used in datasheet */ | |
65 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
66 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
67 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ | |
68 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
69 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
70 | ||
71 | /* | |
72 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
73 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
74 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. | |
75 | * The Linux BASE_BAUD define should match this configuration. | |
76 | * baseBaud = cpuClock/(uartDivisor*16) | |
77 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
78 | * set Linux BASE_BAUD to 403200. | |
79 | */ | |
80 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
81 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ | |
82 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
83 | #define CONFIG_SYS_BASE_BAUD 691200 | |
84 | ||
85 | /* | |
86 | * I2C stuff | |
87 | */ | |
ea818dbb | 88 | #define CONFIG_SYS_I2C |
880540de DE |
89 | #define CONFIG_SYS_I2C_PPC4XX |
90 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
91 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
92 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
b46226bd | 93 | #define CONFIG_SYS_I2C_IHS |
a605ea7e | 94 | |
e50e8968 | 95 | #define CONFIG_SYS_I2C_SPEED 400000 |
b46226bd | 96 | #define CONFIG_SYS_SPD_BUS_NUM 4 |
e50e8968 DE |
97 | |
98 | #define CONFIG_PCA953X /* NXP PCA9554 */ | |
99 | #define CONFIG_PCA9698 /* NXP PCA9698 */ | |
100 | ||
b46226bd DE |
101 | #define CONFIG_SYS_I2C_IHS_CH0 |
102 | #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 | |
103 | #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F | |
104 | #define CONFIG_SYS_I2C_IHS_CH1 | |
105 | #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 | |
106 | #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F | |
107 | #define CONFIG_SYS_I2C_IHS_CH2 | |
108 | #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 | |
109 | #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F | |
110 | #define CONFIG_SYS_I2C_IHS_CH3 | |
111 | #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 | |
112 | #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F | |
113 | ||
a605ea7e DE |
114 | /* |
115 | * Software (bit-bang) I2C driver configuration | |
116 | */ | |
e50e8968 DE |
117 | #define CONFIG_SYS_I2C_SOFT |
118 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
119 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
120 | #define I2C_SOFT_DECLARATIONS2 | |
121 | #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 | |
122 | #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F | |
123 | #define I2C_SOFT_DECLARATIONS3 | |
124 | #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 | |
125 | #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F | |
126 | #define I2C_SOFT_DECLARATIONS4 | |
127 | #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 | |
128 | #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F | |
129 | ||
b46226bd DE |
130 | #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} |
131 | #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} | |
132 | #define CONFIG_SYS_DP501_I2C {0, 1, 2, 3} | |
a605ea7e DE |
133 | |
134 | #ifndef __ASSEMBLY__ | |
e50e8968 DE |
135 | void fpga_gpio_set(unsigned int bus, int pin); |
136 | void fpga_gpio_clear(unsigned int bus, int pin); | |
137 | int fpga_gpio_get(unsigned int bus, int pin); | |
a605ea7e DE |
138 | #endif |
139 | ||
140 | #define I2C_ACTIVE { } | |
141 | #define I2C_TRISTATE { } | |
e50e8968 DE |
142 | #define I2C_READ \ |
143 | (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) | |
144 | #define I2C_SDA(bit) \ | |
145 | do { \ | |
146 | if (bit) \ | |
147 | fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ | |
148 | else \ | |
149 | fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ | |
150 | } while (0) | |
151 | #define I2C_SCL(bit) \ | |
152 | do { \ | |
153 | if (bit) \ | |
154 | fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ | |
155 | else \ | |
156 | fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ | |
157 | } while (0) | |
a605ea7e DE |
158 | #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ |
159 | ||
160 | /* | |
161 | * FLASH organization | |
162 | */ | |
163 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
164 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
165 | ||
166 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
167 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
168 | ||
169 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
170 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ | |
171 | ||
172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ | |
173 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ | |
174 | ||
175 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ | |
a605ea7e DE |
176 | |
177 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ | |
178 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ | |
179 | ||
180 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
181 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
182 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) | |
183 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
184 | ||
185 | /* Address and size of Redundant Environment Sector */ | |
186 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
187 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
188 | #endif | |
189 | ||
190 | /* | |
191 | * PPC405 GPIO Configuration | |
192 | */ | |
193 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ | |
194 | { \ | |
195 | /* GPIO Core 0 */ \ | |
196 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
197 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
198 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
199 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
200 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
201 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
202 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
203 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ | |
204 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
205 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
206 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
207 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
208 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
209 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
210 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
211 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
212 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
213 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
214 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
215 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
216 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
217 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
218 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
219 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
220 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
221 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
222 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
223 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
224 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
225 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
226 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
227 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
228 | } \ | |
229 | } | |
230 | ||
231 | /* | |
232 | * Definitions for initial stack pointer and data area (in data cache) | |
233 | */ | |
234 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
235 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
236 | ||
237 | /* On Chip Memory location */ | |
238 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
239 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
240 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ | |
b39d1213 | 241 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE |
a605ea7e | 242 | |
a605ea7e | 243 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
b39d1213 | 244 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
a605ea7e DE |
245 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
246 | ||
247 | /* | |
248 | * External Bus Controller (EBC) Setup | |
249 | */ | |
250 | ||
251 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
252 | #define CONFIG_SYS_EBC_PB0AP 0xa382a880 | |
253 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 | |
254 | ||
255 | /* Memory Bank 1 (NVRAM) initializatio */ | |
256 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 | |
257 | #define CONFIG_SYS_EBC_PB1CR 0xFB858000 | |
258 | ||
2da0fc0d DE |
259 | /* Memory Bank 2 (FPGA0) initialization */ |
260 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 | |
a605ea7e | 261 | #define CONFIG_SYS_EBC_PB2AP 0x02825080 |
2da0fc0d DE |
262 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000) |
263 | ||
264 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE | |
265 | #define CONFIG_SYS_FPGA_DONE(k) 0x0010 | |
a605ea7e | 266 | |
2da0fc0d | 267 | #define CONFIG_SYS_FPGA_COUNT 1 |
a605ea7e | 268 | |
e50e8968 | 269 | #define CONFIG_SYS_MCLINK_MAX 3 |
aba27acf | 270 | |
e50e8968 DE |
271 | #define CONFIG_SYS_FPGA_PTR \ |
272 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } | |
aba27acf | 273 | |
a605ea7e DE |
274 | /* Memory Bank 3 (Latches) initialization */ |
275 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 | |
276 | #define CONFIG_SYS_EBC_PB3AP 0x02025080 | |
277 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 | |
278 | ||
279 | #define CONFIG_SYS_LATCH0_RESET 0xffef | |
280 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
281 | #define CONFIG_SYS_LATCH1_RESET 0xffff | |
282 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
283 | ||
2da0fc0d DE |
284 | /* |
285 | * OSD Setup | |
286 | */ | |
287 | #define CONFIG_SYS_MPC92469AC | |
e50e8968 | 288 | #define CONFIG_SYS_OSD_SCREENS 1 |
edfe9fea DE |
289 | #define CONFIG_SYS_DP501_DIFFERENTIAL |
290 | #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ | |
e50e8968 DE |
291 | |
292 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
293 | #define CONFIG_BITBANGMII_MULTI | |
2da0fc0d | 294 | |
a605ea7e | 295 | #endif /* __CONFIG_H */ |