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ba94a1bb WD |
1 | /* |
2 | * (C) Copyright 2005-2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2003 | |
6 | * Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl | |
7 | * | |
8 | * Configuation settings for the IXDPG425 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* | |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | #define CONFIG_IXP425 1 /* This is an IXP425 CPU */ | |
37 | #define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */ | |
38 | ||
39 | #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ | |
40 | #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ | |
41 | ||
42 | /* | |
43 | * Ethernet | |
44 | */ | |
45 | #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ | |
46 | #define CONFIG_NET_MULTI 1 | |
47 | #define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */ | |
48 | #define CONFIG_HAS_ETH1 | |
49 | #define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */ | |
50 | #define CONFIG_MII 1 /* MII PHY management */ | |
6d0f6bcf | 51 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
ba94a1bb WD |
52 | |
53 | /* | |
54 | * Misc configuration options | |
55 | */ | |
ba94a1bb WD |
56 | |
57 | #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ | |
6d0f6bcf | 58 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ |
ba94a1bb WD |
59 | |
60 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
61 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
62 | #define CONFIG_INITRD_TAG 1 | |
63 | ||
64 | /* | |
65 | * Size of malloc() pool | |
66 | */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
ba94a1bb WD |
68 | |
69 | /* allow to overwrite serial and ethaddr */ | |
70 | #define CONFIG_ENV_OVERWRITE | |
71 | ||
930590f3 | 72 | #define CONFIG_IXP_SERIAL |
ba94a1bb | 73 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 74 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ |
ba94a1bb | 75 | |
1d2c6bc4 | 76 | |
7f5c0157 JL |
77 | /* |
78 | * BOOTP options | |
79 | */ | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | ||
85 | ||
1d2c6bc4 JL |
86 | /* |
87 | * Command line configuration. | |
88 | */ | |
89 | #include <config_cmd_default.h> | |
90 | ||
91 | #define CONFIG_CMD_DHCP | |
92 | #define CONFIG_CMD_ELF | |
93 | #define CONFIG_CMD_NET | |
94 | #define CONFIG_CMD_MII | |
95 | #define CONFIG_CMD_PING | |
96 | ||
ba94a1bb WD |
97 | |
98 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
99 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
100 | ||
101 | /* | |
102 | * Miscellaneous configurable options | |
103 | */ | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
105 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
106 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
107 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
108 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
109 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ba94a1bb | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
112 | #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ | |
113 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ | |
ba94a1bb | 114 | |
973af335 | 115 | #define CONFIG_IXP425_TIMER_CLK 66666666 |
6d0f6bcf | 116 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ba94a1bb WD |
117 | |
118 | /* valid baudrates */ | |
6d0f6bcf | 119 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
ba94a1bb WD |
120 | |
121 | /* | |
122 | * Stack sizes | |
123 | * | |
124 | * The stack sizes are set up in start.S using the settings below | |
125 | */ | |
126 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
127 | #ifdef CONFIG_USE_IRQ | |
128 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
129 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
130 | #endif | |
131 | ||
132 | /*************************************************************** | |
133 | * Platform/Board specific defines start here. | |
134 | ***************************************************************/ | |
135 | ||
136 | /*----------------------------------------------------------------------- | |
137 | * Default configuration (environment varibles...) | |
138 | *----------------------------------------------------------------------*/ | |
139 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 140 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
ba94a1bb WD |
141 | "echo" |
142 | ||
143 | #undef CONFIG_BOOTARGS | |
144 | ||
145 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
146 | "netdev=eth0\0" \ | |
147 | "hostname=ixdpg425\0" \ | |
148 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
149 | "nfsroot=${serverip}:${rootpath}\0" \ | |
150 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
151 | "addip=setenv bootargs ${bootargs} " \ | |
152 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
153 | ":${hostname}:${netdev}:off panic=1\0" \ | |
154 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
155 | "flash_nfs=run nfsargs addip addtty;" \ | |
156 | "bootm ${kernel_addr}\0" \ | |
157 | "flash_self=run ramargs addip addtty;" \ | |
158 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
159 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
160 | "bootm\0" \ | |
161 | "rootpath=/opt/eldk/arm\0" \ | |
162 | "bootfile=/tftpboot/ixdpg425/uImage\0" \ | |
163 | "kernel_addr=50080000\0" \ | |
164 | "ramdisk_addr=50200000\0" \ | |
165 | "load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \ | |
166 | "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \ | |
167 | "cp.b 100000 50000000 40000;" \ | |
168 | "setenv filesize;saveenv\0" \ | |
d8ab58b2 | 169 | "upd=run load update\0" \ |
ba94a1bb WD |
170 | "" |
171 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
172 | ||
173 | /* | |
174 | * Physical Memory Map | |
175 | */ | |
176 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ | |
177 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
178 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
179 | ||
973af335 MS |
180 | #define CONFIG_SYS_TEXT_BASE 0x50000000 |
181 | ||
ba94a1bb WD |
182 | #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ |
183 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | |
184 | #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ | |
185 | #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ | |
186 | ||
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_DRAM_BASE 0x00000000 |
188 | #define CONFIG_SYS_DRAM_SIZE 0x01000000 | |
ba94a1bb | 189 | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
192 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
ba94a1bb WD |
193 | |
194 | /* | |
195 | * Expansion bus settings | |
196 | */ | |
6d0f6bcf | 197 | #define CONFIG_SYS_EXP_CS0 0xbcd23c42 |
ba94a1bb WD |
198 | |
199 | /* | |
200 | * SDRAM settings | |
201 | */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_SDR_CONFIG 0x18 |
203 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
204 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a | |
ba94a1bb WD |
205 | |
206 | /* | |
207 | * FLASH and environment organization | |
208 | */ | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
210 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
ba94a1bb | 211 | |
6d0f6bcf | 212 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 213 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
5a1aceb0 | 214 | #define CONFIG_ENV_IS_IN_FLASH 1 |
ba94a1bb | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
217 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
ba94a1bb | 218 | |
6d0f6bcf | 219 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
ba94a1bb | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ |
ba94a1bb | 222 | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
224 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
ba94a1bb | 225 | |
6d0f6bcf | 226 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
ba94a1bb | 227 | |
0e8d1586 JCPV |
228 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
229 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) | |
230 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
ba94a1bb WD |
231 | |
232 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
233 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
234 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
ba94a1bb WD |
235 | |
236 | /* | |
237 | * GPIO settings | |
238 | */ | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_GPIO_PCI_INTA_N 6 |
240 | #define CONFIG_SYS_GPIO_PCI_INTB_N 7 | |
241 | #define CONFIG_SYS_GPIO_SWITCH_RESET_N 8 | |
242 | #define CONFIG_SYS_GPIO_SLIC_RESET_N 13 | |
243 | #define CONFIG_SYS_GPIO_PCI_CLK 14 | |
244 | #define CONFIG_SYS_GPIO_EXTBUS_CLK 15 | |
ba94a1bb WD |
245 | |
246 | /* | |
247 | * Cache Configuration | |
248 | */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
ba94a1bb | 250 | |
973af335 MS |
251 | /* additions for new relocation code, must be added to all boards */ |
252 | #define CONFIG_SYS_SDRAM_BASE 0 | |
253 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
254 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
255 | ||
ba94a1bb | 256 | #endif /* __CONFIG_H */ |