[thirdparty/u-boot.git] / include / configs / jupiter.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_JUPITER		1	/* ... on Jupiter board */
#define CONFIG_DISPLAY_BOARDINFO

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFF00000	boot high (standard configuration)
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_BOARD_EARLY_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F	1

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
/*#define CONFIG_PCI		*/

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_MII		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#if defined(CONFIG_PCI)
#define CODFIG_CMD_PCI
#endif


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
		"${baudrate}\0"						\
	"contyp=ttyS0\0"						\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/jupiter/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */

#if 0
/* pass open firmware flat tree */
#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 8)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
#endif

#if 0
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
#define CONFIG_SYS_ALT_MEMTEST		1

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
2605e90b HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2605e90b HS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
b2a6dfe4	16	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
2605e90b	17	#define CONFIG_JUPITER 1 /* ... on Jupiter board */
50301a5a	18	#define CONFIG_DISPLAY_BOARDINFO
2605e90b	19
2ae18241 WD	20	/*
	21	* Valid values for CONFIG_SYS_TEXT_BASE are:
	22	* 0xFFF00000 boot high (standard configuration)
	23	* 0x00100000 boot from RAM (for testing only)
	24	*/
	25	#ifndef CONFIG_SYS_TEXT_BASE
	26	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	27	#endif
	28
6d0f6bcf	29	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
2605e90b HS	30
	31	#define CONFIG_BOARD_EARLY_INIT_R 1
	32	#define CONFIG_BOARD_EARLY_INIT_F 1
	33
31d82672 BB	34	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	35
2605e90b HS	36	/*
	37	* Serial console configuration
	38	*/
	39	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	40	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	41	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
2605e90b HS	42
	43	/*
	44	* PCI Mapping:
	45	* 0x40000000 - 0x4fffffff - PCI Memory
	46	* 0x50000000 - 0x50ffffff - PCI IO Space
	47	*/
769104c9	48	/#define CONFIG_PCI /
2605e90b HS	49
	50	#if defined(CONFIG_PCI)
	51	#define CONFIG_PCI_PNP 1
	52	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	53	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2605e90b HS	54
	55	#define CONFIG_PCI_MEM_BUS 0x40000000
	56	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	57	#define CONFIG_PCI_MEM_SIZE 0x10000000
	58
	59	#define CONFIG_PCI_IO_BUS 0x50000000
	60	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	61	#define CONFIG_PCI_IO_SIZE 0x01000000
2605e90b HS	62	#endif
2605e90b HS	63
6d0f6bcf	64	#define CONFIG_SYS_XLB_PIPELINING 1
2605e90b	65
2605e90b	66	#define CONFIG_MII 1
6d0f6bcf	67	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
2605e90b HS	68
	69	/* Partitions */
	70	#define CONFIG_MAC_PARTITION
	71	#define CONFIG_DOS_PARTITION
	72	#define CONFIG_ISO_PARTITION
	73
	74	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	75
bc234c12	76
7f5c0157 JL	77	/*
	78	* BOOTP options
	79	*/
	80	#define CONFIG_BOOTP_BOOTFILESIZE
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_GATEWAY
	83	#define CONFIG_BOOTP_HOSTNAME
	84
	85
2605e90b	86	/*
bc234c12	87	* Command line configuration.
2605e90b	88	*/
2605e90b	89
7f5c0157 JL	90	#if defined(CONFIG_PCI)
	91	#define CODFIG_CMD_PCI
	92	#endif
	93
2605e90b HS	94
	95	/*
	96	* Autobooting
	97	*/
	98	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	99
	100	#define CONFIG_PREBOOT "echo;" \
32bf3d14	101	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
2605e90b HS	102	"echo"
	103
	104	#undef CONFIG_BOOTARGS
	105
	106	#define CONFIG_EXTRA_ENV_SETTINGS \
	107	"netdev=eth0\0" \
	108	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	109	"nfsroot=${serverip}:${rootpath}\0" \
	110	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	111	"addip=setenv bootargs ${bootargs} " \
	112	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	113	":${hostname}:${netdev}:off panic=1\0" \
a7090b99	114	"flash_nfs=run nfsargs addip addcons;" \
2605e90b HS	115	"bootm ${kernel_addr}\0" \
	116	"flash_self=run ramargs addip;" \
	117	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
a7090b99	118	"addcons=setenv bootargs ${bootargs} console=${contyp}," \
8502e30a HS	119	"${baudrate}\0" \
8502e30a HS	120	"contyp=ttyS0\0" \
a7090b99	121	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
8502e30a HS	122	"bootm\0" \
8502e30a HS	123	"rootpath=/opt/eldk/ppc_6xx\0" \
2605e90b HS	124	"bootfile=/tftpboot/jupiter/uImage\0" \
	125	""
	126
	127	#define CONFIG_BOOTCOMMAND "run flash_self"
	128
	129	/*
	130	* IPB Bus clocking configuration.
	131	*/
6d0f6bcf	132	#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
2605e90b HS	133
	134	#if 0
	135	/* pass open firmware flat tree */
2605e90b HS	136	#define OF_CPU "PowerPC,5200@0"
	137	#define OF_SOC "soc5200@f0000000"
	138	#define OF_TBCLK (bd->bi_busfreq / 8)
	139	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	140	#endif
	141
	142	#if 0
	143	/*
	144	* I2C configuration
	145	*/
	146	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	147	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
2605e90b	148
6d0f6bcf JCPV	149	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	150	#define CONFIG_SYS_I2C_SLAVE 0x7F
2605e90b HS	151
	152	/*
	153	* EEPROM configuration
	154	*/
6d0f6bcf JCPV	155	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	156	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	157	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	158	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
2605e90b HS	159	#endif
	160
	161	/*
	162	* Flash configuration
	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_SIZE 0x01000000
2605e90b	166
6d0f6bcf	167	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
2605e90b	168
14d0a02a	169	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
2605e90b	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	172	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
2605e90b	173
6d0f6bcf	174	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
2605e90b	175
00b1883a	176	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_CFI
	178	#define CONFIG_SYS_FLASH_EMPTY_INFO
	179	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	180	#define CONFIG_SYS_UPDATE_FLASH_SIZE 1
	181	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
2605e90b HS	182
	183	/*
	184	* Environment settings
	185	*/
5a1aceb0	186	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	187	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	188	#define CONFIG_ENV_SECT_SIZE 0x20000
2605e90b HS	189	#define CONFIG_ENV_OVERWRITE 1
2605e90b HS	190
8502e30a	191	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	192	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	193	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
8502e30a	194
2605e90b HS	195	/*
	196	* Memory map
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_MBAR 0xF0000000
	199	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	200	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
2605e90b HS	201
2605e90b HS	202	/* Use SRAM until RAM will be available */
6d0f6bcf	203	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	204	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
2605e90b HS	205
2605e90b HS	206
25ddd1fb	207	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	208	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
2605e90b	209
14d0a02a	210	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	211	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	212	# define CONFIG_SYS_RAMBOOT 1
2605e90b HS	213	#endif
2605e90b HS	214
6d0f6bcf JCPV	215	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	216	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	217	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
2605e90b HS	218
	219	/*
	220	* Ethernet configuration
	221	*/
	222	#define CONFIG_MPC5xxx_FEC 1
86321fc1	223	#define CONFIG_MPC5xxx_FEC_MII100
2605e90b	224	/*
86321fc1	225	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
2605e90b	226	*/
86321fc1	227	/* #define CONFIG_MPC5xxx_FEC_MII10 */
2605e90b HS	228	#define CONFIG_PHY_ADDR 0x00
	229
	230	/*
	231	* GPIO configuration
	232	*/
6d0f6bcf	233	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
2605e90b HS	234
	235	/*
	236	* Miscellaneous configurable options
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8502e30a HS	239
8502e30a HS	240	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
bc234c12	241	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	242	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
2605e90b	243	#else
6d0f6bcf	244	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
2605e90b	245	#endif
6d0f6bcf JCPV	246	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	247	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	248	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
2605e90b	249
6d0f6bcf JCPV	250	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	251	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	252	#define CONFIG_SYS_ALT_MEMTEST 1
2605e90b	253
6d0f6bcf	254	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
2605e90b	255
6d0f6bcf	256	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
bc234c12	257	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	258	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
bc234c12 JL	259	#endif
bc234c12 JL	260
2605e90b HS	261	/*
	262	* Various low-level settings
	263	*/
6d0f6bcf JCPV	264	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	265	#define CONFIG_SYS_HID0_FINAL HID0_ICE
2605e90b	266
6d0f6bcf JCPV	267	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	268	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	269	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	270	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	271	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
2605e90b	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	274	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
2605e90b	275
6d0f6bcf	276	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
2605e90b HS	277
2605e90b HS	278	#endif /* __CONFIG_H */