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1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /************************************************************************ | |
27 | * katmai.h - configuration for AMCC Katmai (440SPe) | |
28 | ***********************************************************************/ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /*----------------------------------------------------------------------- | |
34 | * High Level Configuration Options | |
35 | *----------------------------------------------------------------------*/ | |
36 | #define CONFIG_KATMAI 1 /* Board is Katmai */ | |
37 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
38 | #define CONFIG_440 1 /* ... PPC440 family */ | |
39 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
40 | #undef CFG_DRAM_TEST /* Disable-takes long time */ | |
41 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
42 | ||
43 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
44 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ | |
45 | #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ | |
46 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
47 | ||
48 | /*----------------------------------------------------------------------- | |
49 | * Base addresses -- Note these are effective addresses where the | |
50 | * actual resources get mapped (not physical addresses) | |
51 | *----------------------------------------------------------------------*/ | |
52 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
53 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ | |
54 | ||
55 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
56 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ | |
57 | #define CFG_MONITOR_BASE TEXT_BASE | |
58 | #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ | |
59 | #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ | |
60 | ||
61 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ | |
62 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
63 | #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE | |
64 | ||
65 | #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ | |
66 | #define CFG_PCIE_MEMSIZE 0x01000000 | |
67 | #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ | |
68 | ||
69 | #define CFG_PCIE0_CFGBASE 0xc0000000 | |
70 | #define CFG_PCIE0_XCFGBASE 0xc0000400 | |
71 | #define CFG_PCIE1_CFGBASE 0xc0001000 | |
72 | #define CFG_PCIE1_XCFGBASE 0xc0001400 | |
73 | #define CFG_PCIE2_CFGBASE 0xc0002000 | |
74 | #define CFG_PCIE2_XCFGBASE 0xc0002400 | |
75 | ||
76 | /* System RAM mapped to PCI space */ | |
77 | #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE | |
78 | #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE | |
79 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
80 | ||
81 | #define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ | |
82 | ||
83 | /*----------------------------------------------------------------------- | |
84 | * Initial RAM & stack pointer (placed in internal SRAM) | |
85 | *----------------------------------------------------------------------*/ | |
86 | #define CFG_TEMP_STACK_OCM 1 | |
87 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
88 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ | |
89 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
90 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
91 | ||
92 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
93 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
94 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
95 | ||
96 | /*----------------------------------------------------------------------- | |
97 | * Serial Port | |
98 | *----------------------------------------------------------------------*/ | |
99 | #define CONFIG_SERIAL_MULTI 1 | |
100 | #undef CONFIG_UART1_CONSOLE | |
101 | #undef CFG_EXT_SERIAL_CLOCK | |
102 | #define CONFIG_BAUDRATE 115200 | |
103 | #define CFG_BAUDRATE_TABLE \ | |
104 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
105 | ||
106 | /*----------------------------------------------------------------------- | |
107 | * DDR SDRAM | |
108 | *----------------------------------------------------------------------*/ | |
109 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ | |
ba58e4c9 | 110 | #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ |
2721a68a | 111 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
4745acaa | 112 | #undef CONFIG_STRESS |
4745acaa SR |
113 | |
114 | /*----------------------------------------------------------------------- | |
115 | * I2C | |
116 | *----------------------------------------------------------------------*/ | |
117 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
118 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
119 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ | |
120 | #define CFG_I2C_SLAVE 0x7F | |
121 | ||
122 | #define CONFIG_I2C_MULTI_BUS | |
123 | #define CONFIG_I2C_CMD_TREE | |
124 | #define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */ | |
125 | ||
126 | #define IIC0_BOOTPROM_ADDR 0x50 | |
127 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 | |
128 | ||
129 | #define CFG_I2C_MULTI_EEPROMS | |
130 | #define CFG_I2C_EEPROM_ADDR (0x50) | |
131 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
132 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
133 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
134 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
135 | ||
136 | /* I2C RTC */ | |
137 | #define CONFIG_RTC_M41T11 1 | |
138 | #define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */ | |
139 | #define CFG_I2C_RTC_ADDR 0x68 | |
140 | #define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
141 | ||
142 | /* I2C DTT */ | |
143 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ | |
144 | #define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */ | |
145 | /* | |
146 | * standard dtt sensor configuration - bottom bit will determine local or | |
147 | * remote sensor of the ADM1021, the rest determines index into | |
148 | * CFG_DTT_ADM1021 array below. | |
149 | */ | |
150 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
151 | ||
152 | /* | |
153 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). | |
154 | * there will be one entry in this array for each two (dummy) sensors in | |
155 | * CONFIG_DTT_SENSORS. | |
156 | * | |
157 | * For Katmai board: | |
158 | * - only one ADM1021 | |
159 | * - i2c addr 0x18 | |
160 | * - conversion rate 0x02 = 0.25 conversions/second | |
161 | * - ALERT ouput disabled | |
162 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
163 | * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg | |
164 | */ | |
165 | #define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } | |
166 | ||
167 | /*----------------------------------------------------------------------- | |
168 | * Environment | |
169 | *----------------------------------------------------------------------*/ | |
170 | #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ | |
171 | ||
172 | #define CONFIG_PREBOOT "echo;" \ | |
173 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
174 | "echo" | |
175 | ||
176 | #undef CONFIG_BOOTARGS | |
177 | ||
178 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
179 | "netdev=eth0\0" \ | |
180 | "hostname=katmai\0" \ | |
181 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
182 | "nfsroot=${serverip}:${rootpath}\0" \ | |
183 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
184 | "addip=setenv bootargs ${bootargs} " \ | |
185 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
186 | ":${hostname}:${netdev}:off panic=1\0" \ | |
187 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
188 | "flash_nfs=run nfsargs addip addtty;" \ | |
189 | "bootm ${kernel_addr}\0" \ | |
190 | "flash_self=run ramargs addip addtty;" \ | |
191 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
192 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
193 | "bootm\0" \ | |
194 | "rootpath=/opt/eldk/ppc_4xx\0" \ | |
195 | "bootfile=katmai/uImage\0" \ | |
196 | "kernel_addr=fff10000\0" \ | |
197 | "ramdisk_addr=fff20000\0" \ | |
198 | "initrd_high=30000000\0" \ | |
199 | "load=tftp 200000 katmai/u-boot.bin\0" \ | |
200 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ | |
201 | "cp.b ${fileaddr} fffc0000 ${filesize};" \ | |
202 | "setenv filesize;saveenv\0" \ | |
203 | "upd=run load;run update\0" \ | |
204 | "kozio=bootm ffc60000\0" \ | |
205 | "" | |
206 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
207 | ||
208 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
209 | ||
210 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
211 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
212 | ||
213 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
214 | CFG_CMD_ASKENV | \ | |
215 | CFG_CMD_EEPROM | \ | |
216 | CFG_CMD_DATE | \ | |
217 | CFG_CMD_DHCP | \ | |
218 | CFG_CMD_DIAG | \ | |
219 | CFG_CMD_DTT | \ | |
220 | CFG_CMD_ELF | \ | |
221 | CFG_CMD_EXT2 | \ | |
222 | CFG_CMD_FAT | \ | |
223 | CFG_CMD_I2C | \ | |
224 | CFG_CMD_IRQ | \ | |
225 | CFG_CMD_MII | \ | |
226 | CFG_CMD_NET | \ | |
227 | CFG_CMD_NFS | \ | |
228 | CFG_CMD_PCI | \ | |
229 | CFG_CMD_PING | \ | |
230 | CFG_CMD_REGINFO | \ | |
231 | CFG_CMD_SDRAM) | |
232 | ||
233 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
234 | #include <cmd_confdefs.h> | |
235 | ||
236 | #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ | |
237 | #define CONFIG_MII 1 /* MII PHY management */ | |
238 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
239 | #define CONFIG_HAS_ETH0 | |
240 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
241 | #define CONFIG_PHY_RESET_DELAY 1000 | |
242 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
243 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
244 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
245 | ||
246 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
247 | #define CONFIG_NET_MULTI /* needed for NetConsole */ | |
248 | ||
249 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
250 | ||
251 | /* | |
252 | * Miscellaneous configurable options | |
253 | */ | |
254 | #define CFG_LONGHELP /* undef to save memory */ | |
255 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
256 | ||
257 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
258 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
259 | #else | |
260 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
261 | #endif | |
262 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
263 | #define CFG_MAXARGS 16 /* max number of command args */ | |
264 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
265 | ||
266 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
267 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
268 | ||
269 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
270 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
271 | ||
272 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
273 | ||
274 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
275 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
276 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
277 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
278 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
279 | ||
280 | #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ | |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * FLASH related | |
284 | *----------------------------------------------------------------------*/ | |
285 | #define CFG_FLASH_CFI | |
286 | #define CFG_FLASH_CFI_DRIVER | |
287 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
288 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
289 | ||
290 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} | |
291 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
292 | #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ | |
293 | ||
294 | #undef CFG_FLASH_CHECKSUM | |
295 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
296 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
297 | ||
298 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
299 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) | |
300 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
301 | ||
302 | /* Address and size of Redundant Environment Sector */ | |
303 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
304 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
305 | ||
306 | /*----------------------------------------------------------------------- | |
307 | * PCI stuff | |
308 | *----------------------------------------------------------------------- | |
309 | */ | |
310 | /* General PCI */ | |
311 | #define CONFIG_PCI /* include pci support */ | |
312 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
313 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
314 | #undef CONFIG_PCI_CONFIG_HOST_BRIDGE | |
315 | ||
316 | /* Board-specific PCI */ | |
317 | #define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ | |
318 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ | |
319 | #undef CFG_PCI_MASTER_INIT | |
320 | ||
321 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
322 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
323 | /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ | |
324 | ||
325 | /* | |
326 | * NETWORK Support (PCI): | |
327 | */ | |
328 | /* Support for Intel 82557/82559/82559ER chips. */ | |
329 | #define CONFIG_EEPRO100 | |
330 | ||
331 | /*----------------------------------------------------------------------- | |
332 | * Xilinx System ACE support | |
333 | *----------------------------------------------------------------------*/ | |
334 | #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ | |
335 | #define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ | |
336 | #define CFG_SYSTEMACE_BASE CFG_ACE_BASE | |
337 | #define CONFIG_DOS_PARTITION 1 | |
338 | ||
339 | /*----------------------------------------------------------------------- | |
340 | * External Bus Controller (EBC) Setup | |
341 | *----------------------------------------------------------------------*/ | |
342 | ||
343 | /* Memory Bank 0 (Flash) initialization */ | |
344 | #define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
345 | EBC_BXAP_TWT_ENCODE(7) | \ | |
346 | EBC_BXAP_BCE_DISABLE | \ | |
347 | EBC_BXAP_BCT_2TRANS | \ | |
348 | EBC_BXAP_CSN_ENCODE(0) | \ | |
349 | EBC_BXAP_OEN_ENCODE(0) | \ | |
350 | EBC_BXAP_WBN_ENCODE(0) | \ | |
351 | EBC_BXAP_WBF_ENCODE(0) | \ | |
352 | EBC_BXAP_TH_ENCODE(0) | \ | |
353 | EBC_BXAP_RE_DISABLED | \ | |
354 | EBC_BXAP_SOR_DELAYED | \ | |
355 | EBC_BXAP_BEM_WRITEONLY | \ | |
356 | EBC_BXAP_PEN_DISABLED) | |
357 | #define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \ | |
358 | EBC_BXCR_BS_16MB | \ | |
359 | EBC_BXCR_BU_RW | \ | |
360 | EBC_BXCR_BW_16BIT) | |
361 | ||
362 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
363 | #define CFG_EBC_PB1AP 0x7F8FFE80 | |
364 | #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ | |
365 | EBC_BXCR_BS_1MB | \ | |
366 | EBC_BXCR_BU_RW | \ | |
367 | EBC_BXCR_BW_16BIT) | |
368 | ||
369 | /*------------------------------------------------------------------------- | |
370 | * Initialize EBC CONFIG - | |
371 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
372 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
373 | *-------------------------------------------------------------------------*/ | |
374 | #define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \ | |
375 | EBC_CFG_PTD_ENABLE | \ | |
376 | EBC_CFG_RTC_16PERCLK | \ | |
377 | EBC_CFG_ATC_PREVIOUS | \ | |
378 | EBC_CFG_DTC_PREVIOUS | \ | |
379 | EBC_CFG_CTC_PREVIOUS | \ | |
380 | EBC_CFG_OEO_PREVIOUS | \ | |
381 | EBC_CFG_EMC_DEFAULT | \ | |
382 | EBC_CFG_PME_DISABLE | \ | |
383 | EBC_CFG_PR_16) | |
384 | ||
ba58e4c9 SR |
385 | /*----------------------------------------------------------------------- |
386 | * GPIO Setup | |
387 | *----------------------------------------------------------------------*/ | |
388 | #define CFG_GPIO_PCIE_PRESENT0 17 | |
389 | #define CFG_GPIO_PCIE_PRESENT1 21 | |
390 | #define CFG_GPIO_PCIE_PRESENT2 23 | |
391 | #define CFG_GPIO_RS232_FORCEOFF 30 | |
392 | ||
393 | #define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \ | |
394 | GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \ | |
395 | GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \ | |
396 | GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)) | |
397 | #define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) | |
398 | #define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) | |
399 | #define CFG_GPIO_ODR 0 | |
400 | ||
4745acaa SR |
401 | /* |
402 | * For booting Linux, the board info and command line data | |
403 | * have to be in the first 8 MB of memory, since this is | |
404 | * the maximum mapped by the Linux kernel during initialization. | |
405 | */ | |
406 | #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ | |
407 | /*----------------------------------------------------------------------- | |
408 | * Cache Configuration | |
409 | */ | |
410 | #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ | |
411 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
412 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
413 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
414 | #endif | |
415 | ||
416 | /* | |
417 | * Internal Definitions | |
418 | * | |
419 | * Boot Flags | |
420 | */ | |
421 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
422 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
423 | ||
424 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
425 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
426 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
427 | #endif | |
428 | ||
429 | #endif /* __CONFIG_H */ |